drm/amd/display: extended the programming sequence to VFlip as well

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc.c

@@ -1316,6 +1316,9 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 
 		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+			struct pipe_ctx *cur_pipe_ctx;
+			bool is_new_pipe_surface = true;
+
 			if (pipe_ctx->surface != surface)
 				continue;
 			/*lock all the MCPP if blnd is enable for DRR*/
@@ -1324,26 +1327,16 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 							surface_count != context->res_ctx.pool->pipe_count)) &&
 					!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
 				lock_mask = PIPE_LOCK_CONTROL_MPCC_ADDR;
-				core_dc->hwss.pipe_control_lock(
-						core_dc,
-						pipe_ctx,
-						lock_mask,
-						true);
-				}
 			}
-		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
-			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-			struct pipe_ctx *cur_pipe_ctx;
-			bool is_new_pipe_surface = true;
 
-			if (pipe_ctx->surface != surface)
-				continue;
 			if (update_type != UPDATE_TYPE_FAST &&
 				!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
 				lock_mask = PIPE_LOCK_CONTROL_GRAPHICS |
 						PIPE_LOCK_CONTROL_SCL |
 						PIPE_LOCK_CONTROL_BLENDER |
 						PIPE_LOCK_CONTROL_MODE;
+			}
+			if (lock_mask != 0) {
 				core_dc->hwss.pipe_control_lock(
 						core_dc,
 						pipe_ctx,
@@ -1389,7 +1382,7 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 		}
 	}
 
-	if (update_type == UPDATE_TYPE_FAST && (lock_mask == 0))
+	if ((update_type == UPDATE_TYPE_FAST) && lock_mask == 0)
 		return;
 
 	for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {