Commit 939206e7 authored by Matt Porter's avatar Matt Porter Committed by Linus Torvalds

[PATCH] ppc32: Fix dual UICs in 4xx PIC support

Fixes a case where we were not correctly acking the base cascade controller
on PPC4xx.  Patch from Pavel Bartusek <pba@sysgo.com>
Signed-off-by: default avatarMatt Porter <mporter@kernel.crashing.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 2197b58c
...@@ -234,6 +234,9 @@ ppc4xx_uic_disable_and_ack(unsigned int irq) ...@@ -234,6 +234,9 @@ ppc4xx_uic_disable_and_ack(unsigned int irq)
case 1: case 1:
mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit))); mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit)));
#if (NR_UICS == 2)
mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC)));
#endif
#if (NR_UICS > 2) #if (NR_UICS > 2)
mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC); mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
#endif #endif
...@@ -285,6 +288,9 @@ ppc4xx_uic_end(unsigned int irq) ...@@ -285,6 +288,9 @@ ppc4xx_uic_end(unsigned int irq)
break; break;
case 1: case 1:
mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit)); mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit));
#if (NR_UICS == 2)
mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC)));
#endif
#if (NR_UICS > 2) #if (NR_UICS > 2)
mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC); mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
#endif #endif
...@@ -423,7 +429,7 @@ ppc4xx_extpic_init(void) ...@@ -423,7 +429,7 @@ ppc4xx_extpic_init(void)
bit, sense); bit, sense);
#endif #endif
ppc_cached_sense_mask[word] |= ppc_cached_sense_mask[word] |=
(sense & IRQ_SENSE_MASK) << (31 - bit); (~sense & IRQ_SENSE_MASK) << (31 - bit);
ppc_cached_pol_mask[word] |= ppc_cached_pol_mask[word] |=
((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit); ((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit);
switch (word) { switch (word) {
......
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