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Commit 93a9f05a authored by Sanjeev Sharma's avatar Sanjeev Sharma Committed by Greg Kroah-Hartman
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staging:r8190_rtl8256: coding style: Fixed commenting style 

This is a patch to the r8190_rtl8256.c file that fixes
commenting style Error
Signed-off-by: default avatarSanjeev Sharma <Sanjeev_Sharma@mentor.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a82b4b01
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Showing with 21 additions and 31 deletions
drivers/staging/rtl8192u/r8190_rtl8256.c
View file @ 93a9f05a
......@@ -49,9 +49,6 @@ void PHY_SetRF8256Bandwidth(struct net_device *dev , HT_CHANNEL_WIDTH Bandwidth)
rtl8192_phy_SetRFReg(dev,
(RF90_RADIO_PATH_E)eRFPath,
0x0e, bMask12Bits, 0x021);
/* cosa add for sd3's request 01/23/2008
*/
rtl8192_phy_SetRFReg(dev,
(RF90_RADIO_PATH_E)eRFPath,
0x14, bMask12Bits, 0x5ab);
......@@ -61,13 +58,12 @@ void PHY_SetRF8256Bandwidth(struct net_device *dev , HT_CHANNEL_WIDTH Bandwidth)
break;
case HT_CHANNEL_WIDTH_20_40:
if (priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); /* phy para:3ba */
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
//cosa add for sd3's request 01/23/2008
if (priv->chan == 3 || priv->chan == 9)
//I need to set priv->chan whenever current channel changes
/* I need to set priv->chan whenever current channel changes */
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
else
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
......@@ -91,11 +87,12 @@ void PHY_SetRF8256Bandwidth(struct net_device *dev , HT_CHANNEL_WIDTH Bandwidth)
void PHY_RF8256_Config(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
// Initialize general global value
//
// TODO: Extend RF_PATH_C and RF_PATH_D in the future
/* Initialize general global value
*
* TODO: Extend RF_PATH_C and RF_PATH_D in the future
*/
priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
// Config BB and RF
/* Config BB and RF */
phy_RF8256_Config_ParaFile(dev);
}
/*--------------------------------------------------------------------------
......@@ -107,10 +104,6 @@ void PHY_RF8256_Config(struct net_device *dev)
void phy_RF8256_Config_ParaFile(struct net_device *dev)
{
u32 u4RegValue = 0;
//static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A;
//static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B;
//static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C;
//static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
struct r8192_priv *priv = ieee80211_priv(dev);
......@@ -119,19 +112,17 @@ void phy_RF8256_Config_ParaFile(struct net_device *dev)
u32 RF3_Final_Value = 0;
u8 ConstRetryTimes = 5, RetryTimes = 5;
u8 ret = 0;
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
/* Initialize RF */
for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) {
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
pPhyReg = &priv->PHYRegDef[eRFPath];
// Joseph test for shorten RF config
// pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
/*----Store original RFENV control type----*/
/* Joseph test for shorten RF config
* pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
* ----Store original RFENV control type
*/
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
......@@ -150,13 +141,14 @@ void phy_RF8256_Config_ParaFile(struct net_device *dev)
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
/* Set bit number of Address and Data for RF register */
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? */
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
/*----Check RF block (for FPGA platform only)----*/
// TODO: this function should be removed on ASIC , Emily 2007.2.2
/* Check RF block (for FPGA platform only)----
* TODO: this function should be removed on ASIC , Emily 2007.2.2
*/
if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) {
RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
......@@ -231,11 +223,9 @@ void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel)
{
u32 TxAGC = 0;
struct r8192_priv *priv = ieee80211_priv(dev);
//modified by vivi, 20080109
TxAGC = powerlevel;
if (priv->bDynamicTxLowPower == TRUE) {
//cosa 05/22/2008 for scan
if (priv->CustomerID == RT_CID_819x_Netcore)
TxAGC = 0x22;
else
......@@ -251,15 +241,15 @@ void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel)
void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
{
struct r8192_priv *priv = ieee80211_priv(dev);
//Joseph TxPower for 8192 testing
/* Joseph TxPower for 8192 testing */
u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
u8 index = 0;
u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
u8 byte0, byte1, byte2, byte3;
powerBase0 = powerlevel + priv->TxPowerDiff; //OFDM rates
powerBase0 = powerlevel + priv->TxPowerDiff; /* OFDM rates */
powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
powerBase1 = powerlevel; //MCS rates
powerBase1 = powerlevel; /* MCS rates */
powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
for (index = 0; index < 6; index++) {
......@@ -279,7 +269,7 @@ void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
if (byte3 > 0x24)
byte3 = 0x24;
//for tx power track
/* for tx power track */
if (index == 3) {
writeVal_tmp = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
priv->Pwr_Track = writeVal_tmp;
......
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