Commit 9417f703 authored by Kent Russell's avatar Kent Russell Committed by Alex Deucher

drm/amdgpu: Fix Vega20 Perf counter for pcie_bw

The perf counter for Vega20 is 108, instead of 104 which it was on all
previous GPUs, so add a check to use the appropriate value.
Signed-off-by: default avatarKent Russell <kent.russell@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ca9db7d1
...@@ -717,9 +717,15 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, ...@@ -717,9 +717,15 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
return; return;
/* Set the 2 events that we wish to watch, defined above */ /* Set the 2 events that we wish to watch, defined above */
/* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ /* Reg 40 is # received msgs */
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
if (adev->asic_type == CHIP_VEGA20)
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
EVENT1_SEL, 108);
else
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
EVENT1_SEL, 104);
/* Write to enable desired perf counters */ /* Write to enable desired perf counters */
WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
......
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