Commit 946db173 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle

MIPS: CPS: Read CM GCR base from cop0

Rather than patching the start of mips_cps_core_entry to provide the
base address of the CM GCRs, simply read that base address from the cop0
CMGCRBase register, converting from the physical address to an uncached
virtual address.
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Cc: Niklas Cassel <niklas.cassel@axis.com>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11203/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 609cf6f2
...@@ -67,11 +67,9 @@ ...@@ -67,11 +67,9 @@
LEAF(mips_cps_core_entry) LEAF(mips_cps_core_entry)
/* /*
* These first 12 bytes will be patched by cps_smp_setup to load the * These first 4 bytes will be patched by cps_smp_setup to load the
* base address of the CM GCRs into register v1 and the CCA to use into * CCA to use into register s0.
* register s0.
*/ */
.quad 0
.word 0 .word 0
/* Check whether we're here due to an NMI */ /* Check whether we're here due to an NMI */
...@@ -171,6 +169,12 @@ dcache_done: ...@@ -171,6 +169,12 @@ dcache_done:
mtc0 t0, CP0_CONFIG mtc0 t0, CP0_CONFIG
ehb ehb
/* Calculate an uncached address for the CM GCRs */
MFC0 v1, CP0_CMGCRBASE
PTR_SLL v1, v1, 4
PTR_LI t0, UNCAC_BASE
PTR_ADDU v1, v1, t0
/* Enter the coherent domain */ /* Enter the coherent domain */
li t0, 0xff li t0, 0xff
sw t0, GCR_CL_COHERENCE_OFS(v1) sw t0, GCR_CL_COHERENCE_OFS(v1)
......
...@@ -133,11 +133,9 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) ...@@ -133,11 +133,9 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
/* /*
* Patch the start of mips_cps_core_entry to provide: * Patch the start of mips_cps_core_entry to provide:
* *
* v1 = CM base address
* s0 = kseg0 CCA * s0 = kseg0 CCA
*/ */
entry_code = (u32 *)&mips_cps_core_entry; entry_code = (u32 *)&mips_cps_core_entry;
UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
uasm_i_addiu(&entry_code, 16, 0, cca); uasm_i_addiu(&entry_code, 16, 0, cca);
blast_dcache_range((unsigned long)&mips_cps_core_entry, blast_dcache_range((unsigned long)&mips_cps_core_entry,
(unsigned long)entry_code); (unsigned long)entry_code);
......
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