Commit 95e9fd10 authored by Tony Prisk's avatar Tony Prisk

arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices

Bindings for gpio, interrupt controller, power management controller,
timer, realtime clock, serial uart, ehci and uhci controllers and
framebuffer controllers used on the arch-vt8500 platform.

Framebuffer binding also specifies a 'display' node which is required
for determining the lcd panel data.
Signed-off-by: default avatarTony Prisk <linux@prisktech.co.nz>
parent 85814d69
VIA/Wondermedia VT8500 Platforms Device Tree Bindings
---------------------------------------
Boards with the VIA VT8500 SoC shall have the following properties:
Required root node property:
compatible = "via,vt8500";
Boards with the Wondermedia WM8505 SoC shall have the following properties:
Required root node property:
compatible = "wm,wm8505";
Boards with the Wondermedia WM8650 SoC shall have the following properties:
Required root node property:
compatible = "wm,wm8650";
VIA/Wondermedia VT8500 Interrupt Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-intc"
- reg : Should contain 1 register ranges(address and length)
- #interrupt-cells : should be <1>
Example:
intc: interrupt-controller@d8140000 {
compatible = "via,vt8500-intc";
interrupt-controller;
reg = <0xd8140000 0x10000>;
#interrupt-cells = <1>;
};
VIA/Wondermedia VT8500 Power Management Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-pmc"
- reg : Should contain 1 register ranges(address and length)
Example:
pmc@d8130000 {
compatible = "via,vt8500-pmc";
reg = <0xd8130000 0x1000>;
};
VIA/Wondermedia VT8500 Timer
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-timer"
- reg : Should contain 1 register ranges(address and length)
- interrupts : interrupt for the timer
Example:
timer@d8130100 {
compatible = "via,vt8500-timer";
reg = <0xd8130100 0x28>;
interrupts = <36>;
};
Device Tree Clock bindings for arch-vt8500
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
"wm,wm8650-pll-clock" - for a WM8650 PLL clock
"via,vt8500-device-clock" - for a VT/WM device clock
Required properties for PLL clocks:
- reg : shall be the control register offset from PMC base for the pll clock.
- clocks : shall be the input parent clock phandle for the clock. This should
be the reference clock.
- #clock-cells : from common clock binding; shall be set to 0.
Required properties for device clocks:
- clocks : shall be the input parent clock phandle for the clock. This should
be a pll output.
- #clock-cells : from common clock binding; shall be set to 0.
Device Clocks
Device clocks are required to have one or both of the following sets of
properties:
Gated device clocks:
Required properties:
- enable-reg : shall be the register offset from PMC base for the enable
register.
- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
Divisor device clocks:
Required property:
- divisor-reg : shall be the register offset from PMC base for the divisor
register.
Optional property:
- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
if not specified.
For example:
ref25: ref25M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
plla: plla {
#clock-cells = <0>;
compatible = "wm,wm8650-pll-clock";
clocks = <&ref25>;
reg = <0x200>;
};
sdhc: sdhc {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x328>;
divisor-mask = <0x3f>;
enable-reg = <0x254>;
enable-bit = <18>;
};
VIA/Wondermedia VT8500 GPIO Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
or "wm,wm8650-gpio" depending on your SoC
- reg : Should contain 1 register range (address and length)
- #gpio-cells : should be <3>.
1) bank
2) pin number
3) flags - should be 0
Example:
gpio: gpio-controller@d8110000 {
compatible = "via,vt8500-gpio";
gpio-controller;
reg = <0xd8110000 0x10000>;
#gpio-cells = <3>;
};
vibrate {
gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
};
VIA/Wondermedia VT8500 Realtime Clock Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-rtc"
- reg : Should contain 1 register ranges(address and length)
- interrupts : alarm interrupt
Example:
rtc@d8100000 {
compatible = "via,vt8500-rtc";
reg = <0xd8100000 0x10000>;
interrupts = <48>;
};
VIA/Wondermedia VT8500 UART Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-uart"
- reg : Should contain 1 register ranges(address and length)
- interrupts : UART interrupt
- clocks : phandle to the uart source clock (usually a 24Mhz fixed clock)
Example:
uart@d8210000 {
compatible = "via,vt8500-uart";
reg = <0xd8210000 0x1040>;
interrupts = <47>;
clocks = <&ref24>;
};
Generic Platform UHCI Controller
-----------------------------------------------------
Required properties:
- compatible : "platform-uhci"
- reg : Should contain 1 register ranges(address and length)
- interrupts : UHCI controller interrupt
Example:
uhci@d8007b00 {
compatible = "platform-uhci";
reg = <0xd8007b00 0x200>;
interrupts = <43>;
};
VIA/Wondermedia VT8500 EHCI Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-ehci"
- reg : Should contain 1 register ranges(address and length)
- interrupts : ehci controller interrupt
Example:
ehci@d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
interrupts = <43>;
};
......@@ -47,5 +47,7 @@ sirf SiRF Technology, Inc.
st STMicroelectronics
stericsson ST-Ericsson
ti Texas Instruments
via VIA Technologies, Inc.
wlf Wolfson Microelectronics
wm Wondermedia Technologies, Inc.
xlnx Xilinx
VIA VT8500 Framebuffer
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-fb"
- reg : Should contain 1 register ranges(address and length)
- interrupts : framebuffer controller interrupt
- display: a phandle pointing to the display node
Required nodes:
- display: a display node is required to initialize the lcd panel
This should be in the board dts.
- default-mode: a videomode within the display with timing parameters
as specified below.
Example:
fb@d800e400 {
compatible = "via,vt8500-fb";
reg = <0xd800e400 0x400>;
interrupts = <12>;
display = <&display>;
default-mode = <&mode0>;
};
VIA VT8500 Display
-----------------------------------------------------
Required properties (as per of_videomode_helper):
- hactive, vactive: Display resolution
- hfront-porch, hback-porch, hsync-len: Horizontal Display timing parameters
in pixels
vfront-porch, vback-porch, vsync-len: Vertical display timing parameters in
lines
- clock: displayclock in Hz
- bpp: lcd panel bit-depth.
<16> for RGB565, <32> for RGB888
Optional properties (as per of_videomode_helper):
- width-mm, height-mm: Display dimensions in mm
- hsync-active-high (bool): Hsync pulse is active high
- vsync-active-high (bool): Vsync pulse is active high
- interlaced (bool): This is an interlaced mode
- doublescan (bool): This is a doublescan mode
Example:
display: display@0 {
modes {
mode0: mode@0 {
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hfront-porch = <40>;
hsync-len = <0>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <1>;
clock = <0>; /* unused but required */
bpp = <16>; /* non-standard but required */
};
};
};
VIA/Wondermedia Graphics Engine Controller
-----------------------------------------------------
Required properties:
- compatible : "wm,prizm-ge-rops"
- reg : Should contain 1 register ranges(address and length)
Example:
ge_rops@d8050400 {
compatible = "wm,prizm-ge-rops";
reg = <0xd8050400 0x100>;
};
Wondermedia WM8505 Framebuffer
-----------------------------------------------------
Required properties:
- compatible : "wm,wm8505-fb"
- reg : Should contain 1 register ranges(address and length)
- via,display: a phandle pointing to the display node
Required nodes:
- display: a display node is required to initialize the lcd panel
This should be in the board dts. See definition in
Documentation/devicetree/bindings/video/via,vt8500-fb.txt
- default-mode: a videomode node as specified in
Documentation/devicetree/bindings/video/via,vt8500-fb.txt
Example:
fb@d8050800 {
compatible = "wm,wm8505-fb";
reg = <0xd8050800 0x200>;
display = <&display>;
default-mode = <&mode0>;
};
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