Commit 96bdd9ae authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'renesas-dt4-for-v3.18' of...

Merge tag 'renesas-dt4-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Fourth Round of Renesas ARM Based SoC DT Updates for v3.18" from Simon Horman:

* Add r8a7794 SoC and Alt board device tree
* Correct lager memory map
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>

* tag 'renesas-dt4-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: Initial Alt board device tree
  ARM: shmobile: Initial r8a7794 SoC device tree
  ARM: shmobile: lager: correct memory map
parents 87e9d8fd a742795b
......@@ -375,7 +375,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7790-lager.dtb \
r8a7779-marzen.dtb
r8a7779-marzen.dtb \
r8a7794-alt.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
......
......@@ -32,7 +32,7 @@ memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
};
memory@180000000 {
memory@140000000 {
device_type = "memory";
reg = <1 0x40000000 0 0xc0000000>;
};
......
/*
* Device Tree Source for the Alt board
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7794.dtsi"
/ {
model = "Alt";
compatible = "renesas,alt", "renesas,r8a7794";
aliases {
serial0 = &scif2;
};
chosen {
bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
lbsc {
#address-cells = <1>;
#size-cells = <1>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&cmt0 {
status = "ok";
};
&scif2 {
status = "ok";
};
This diff is collapsed.
/*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
#define __DT_BINDINGS_CLOCK_R8A7794_H__
/* CPG */
#define R8A7794_CLK_MAIN 0
#define R8A7794_CLK_PLL0 1
#define R8A7794_CLK_PLL1 2
#define R8A7794_CLK_PLL3 3
#define R8A7794_CLK_LB 4
#define R8A7794_CLK_QSPI 5
#define R8A7794_CLK_SDH 6
#define R8A7794_CLK_SD0 7
#define R8A7794_CLK_Z 8
/* MSTP0 */
#define R8A7794_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7794_CLK_TMU1 11
#define R8A7794_CLK_TMU3 21
#define R8A7794_CLK_TMU2 22
#define R8A7794_CLK_CMT0 24
#define R8A7794_CLK_TMU0 25
/* MSTP2 */
#define R8A7794_CLK_SCIFA2 2
#define R8A7794_CLK_SCIFA1 3
#define R8A7794_CLK_SCIFA0 4
#define R8A7794_CLK_MSIOF2 5
#define R8A7794_CLK_SCIFB0 6
#define R8A7794_CLK_SCIFB1 7
#define R8A7794_CLK_MSIOF1 8
#define R8A7794_CLK_SCIFB2 16
/* MSTP3 */
#define R8A7794_CLK_CMT1 29
/* MSTP5 */
#define R8A7794_CLK_THERMAL 22
#define R8A7794_CLK_PWM 23
/* MSTP7 */
#define R8A7794_CLK_HSCIF2 13
#define R8A7794_CLK_SCIF5 14
#define R8A7794_CLK_SCIF4 15
#define R8A7794_CLK_HSCIF1 16
#define R8A7794_CLK_HSCIF0 17
#define R8A7794_CLK_SCIF3 18
#define R8A7794_CLK_SCIF2 19
#define R8A7794_CLK_SCIF1 20
#define R8A7794_CLK_SCIF0 21
/* MSTP8 */
#define R8A7794_CLK_ETHER 13
/* MSTP9 */
#define R8A7794_CLK_GPIO6 5
#define R8A7794_CLK_GPIO5 7
#define R8A7794_CLK_GPIO4 8
#define R8A7794_CLK_GPIO3 9
#define R8A7794_CLK_GPIO2 10
#define R8A7794_CLK_GPIO1 11
#define R8A7794_CLK_GPIO0 12
/* MSTP11 */
#define R8A7794_CLK_SCIFA3 6
#define R8A7794_CLK_SCIFA4 7
#define R8A7794_CLK_SCIFA5 8
#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment