Commit 9740e001 authored by Claudiu Manoil's avatar Claudiu Manoil Committed by David S. Miller

gianfar: Fix RXICr/TXICr programming for multi-queue mode

The correct behavior is to program the interrupt coalescing regs
(RXICr/TXICr) in accordance with the Rx/Tx Q's "rx/txcoalescing"
flag. That is, if the coalescing flag is 0 for a given Rx/Tx queue
then the corresponding coalescing register should be cleared.
This behavior is correctly implemented for the single-queue mode
(SQ_SG_MODE), but not for the multi-queue mode (MQ_MG_MODE).
This fixes the later case.
Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7cecb523
...@@ -1804,18 +1804,16 @@ void gfar_configure_coalescing(struct gfar_private *priv, ...@@ -1804,18 +1804,16 @@ void gfar_configure_coalescing(struct gfar_private *priv,
if (priv->mode == MQ_MG_MODE) { if (priv->mode == MQ_MG_MODE) {
baddr = &regs->txic0; baddr = &regs->txic0;
for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
if (likely(priv->tx_queue[i]->txcoalescing)) { gfar_write(baddr + i, 0);
gfar_write(baddr + i, 0); if (likely(priv->tx_queue[i]->txcoalescing))
gfar_write(baddr + i, priv->tx_queue[i]->txic); gfar_write(baddr + i, priv->tx_queue[i]->txic);
}
} }
baddr = &regs->rxic0; baddr = &regs->rxic0;
for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
if (likely(priv->rx_queue[i]->rxcoalescing)) { gfar_write(baddr + i, 0);
gfar_write(baddr + i, 0); if (likely(priv->rx_queue[i]->rxcoalescing))
gfar_write(baddr + i, priv->rx_queue[i]->rxic); gfar_write(baddr + i, priv->rx_queue[i]->rxic);
}
} }
} }
} }
......
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