drm/i915/psr: Set frames before SU entry for psr2
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3. v2 : - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo) - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo) - add check ==1 for dpcd_read call (ville) v3 : (Rodrigo) - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU - replace with &= v4 : - change the macro to shift value (jani) - updated register names Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> CC: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1506419953-32605-2-git-send-email-vathsala.nagaraju@intel.com
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