Commit 9830e44f authored by Dave Airlie's avatar Dave Airlie

Merge tag 'vmwgfx-fixes-3.14-2014-02-18' of...

Merge tag 'vmwgfx-fixes-3.14-2014-02-18' of git://people.freedesktop.org/~thomash/linux into drm-fixes

Pull request of 2014-02-18.

Nothing special. The biggest change is adding a couple of command defines and
packing the command data correctly.

* tag 'vmwgfx-fixes-3.14-2014-02-18' of git://people.freedesktop.org/~thomash/linux:
  drm/vmwgfx: Fix command defines and checks
  drm/vmwgfx: Fix possible integer overflow
  drm/vmwgfx: Remove stray const
  drm/vmwgfx: unlock on error path in vmw_execbuf_process()
  drm/vmwgfx: Get maximum mob size from register SVGA_REG_MOB_MAX_SIZE
  drm/vmwgfx: Fix a couple of sparse warnings and errors
parents 560591f1 36e952c1
This diff is collapsed.
...@@ -38,8 +38,11 @@ ...@@ -38,8 +38,11 @@
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) #define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
#define max_t(type, x, y) ((x) > (y) ? (x) : (y)) #define max_t(type, x, y) ((x) > (y) ? (x) : (y))
#define min_t(type, x, y) ((x) < (y) ? (x) : (y))
#define surf_size_struct SVGA3dSize #define surf_size_struct SVGA3dSize
#define u32 uint32 #define u32 uint32
#define u64 uint64_t
#define U32_MAX ((u32)~0U)
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
...@@ -704,8 +707,8 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = { ...@@ -704,8 +707,8 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
static inline u32 clamped_umul32(u32 a, u32 b) static inline u32 clamped_umul32(u32 a, u32 b)
{ {
uint64_t tmp = (uint64_t) a*b; u64 tmp = (u64) a*b;
return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; return (tmp > (u64) U32_MAX) ? U32_MAX : tmp;
} }
static inline const struct svga3d_surface_desc * static inline const struct svga3d_surface_desc *
...@@ -834,7 +837,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format, ...@@ -834,7 +837,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
bool cubemap) bool cubemap)
{ {
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
u32 total_size = 0; u64 total_size = 0;
u32 mip; u32 mip;
for (mip = 0; mip < num_mip_levels; mip++) { for (mip = 0; mip < num_mip_levels; mip++) {
...@@ -847,7 +850,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format, ...@@ -847,7 +850,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
if (cubemap) if (cubemap)
total_size *= SVGA3D_MAX_SURFACE_FACES; total_size *= SVGA3D_MAX_SURFACE_FACES;
return total_size; return (u32) min_t(u64, total_size, (u64) U32_MAX);
} }
......
...@@ -169,10 +169,17 @@ enum { ...@@ -169,10 +169,17 @@ enum {
SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */ SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */
SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
SVGA_REG_TOP = 53, /* Must be 1 more than the last register */ SVGA_REG_CMD_PREPEND_LOW = 53,
SVGA_REG_CMD_PREPEND_HIGH = 54,
SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
SVGA_REG_MOB_MAX_SIZE = 57,
SVGA_REG_TOP = 58, /* Must be 1 more than the last register */
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
/* Next 768 (== 256*3) registers exist for colormap */ /* Next 768 (== 256*3) registers exist for colormap */
......
...@@ -551,8 +551,7 @@ static int vmw_context_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind) ...@@ -551,8 +551,7 @@ static int vmw_context_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind)
cmd->header.size = sizeof(cmd->body); cmd->header.size = sizeof(cmd->body);
cmd->body.cid = bi->ctx->id; cmd->body.cid = bi->ctx->id;
cmd->body.type = bi->i1.shader_type; cmd->body.type = bi->i1.shader_type;
cmd->body.shid = cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
vmw_fifo_commit(dev_priv, sizeof(*cmd)); vmw_fifo_commit(dev_priv, sizeof(*cmd));
return 0; return 0;
...@@ -585,8 +584,7 @@ static int vmw_context_scrub_render_target(struct vmw_ctx_bindinfo *bi, ...@@ -585,8 +584,7 @@ static int vmw_context_scrub_render_target(struct vmw_ctx_bindinfo *bi,
cmd->header.size = sizeof(cmd->body); cmd->header.size = sizeof(cmd->body);
cmd->body.cid = bi->ctx->id; cmd->body.cid = bi->ctx->id;
cmd->body.type = bi->i1.rt_type; cmd->body.type = bi->i1.rt_type;
cmd->body.target.sid = cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
cmd->body.target.face = 0; cmd->body.target.face = 0;
cmd->body.target.mipmap = 0; cmd->body.target.mipmap = 0;
vmw_fifo_commit(dev_priv, sizeof(*cmd)); vmw_fifo_commit(dev_priv, sizeof(*cmd));
...@@ -628,8 +626,7 @@ static int vmw_context_scrub_texture(struct vmw_ctx_bindinfo *bi, ...@@ -628,8 +626,7 @@ static int vmw_context_scrub_texture(struct vmw_ctx_bindinfo *bi,
cmd->body.c.cid = bi->ctx->id; cmd->body.c.cid = bi->ctx->id;
cmd->body.s1.stage = bi->i1.texture_stage; cmd->body.s1.stage = bi->i1.texture_stage;
cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE; cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;
cmd->body.s1.value = cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
vmw_fifo_commit(dev_priv, sizeof(*cmd)); vmw_fifo_commit(dev_priv, sizeof(*cmd));
return 0; return 0;
......
...@@ -667,6 +667,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) ...@@ -667,6 +667,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
dev_priv->memory_size = 512*1024*1024; dev_priv->memory_size = 512*1024*1024;
} }
dev_priv->max_mob_pages = 0; dev_priv->max_mob_pages = 0;
dev_priv->max_mob_size = 0;
if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
uint64_t mem_size = uint64_t mem_size =
vmw_read(dev_priv, vmw_read(dev_priv,
...@@ -676,6 +677,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) ...@@ -676,6 +677,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
dev_priv->prim_bb_mem = dev_priv->prim_bb_mem =
vmw_read(dev_priv, vmw_read(dev_priv,
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
dev_priv->max_mob_size =
vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
} else } else
dev_priv->prim_bb_mem = dev_priv->vram_size; dev_priv->prim_bb_mem = dev_priv->vram_size;
......
...@@ -386,6 +386,7 @@ struct vmw_private { ...@@ -386,6 +386,7 @@ struct vmw_private {
uint32_t max_gmr_ids; uint32_t max_gmr_ids;
uint32_t max_gmr_pages; uint32_t max_gmr_pages;
uint32_t max_mob_pages; uint32_t max_mob_pages;
uint32_t max_mob_size;
uint32_t memory_size; uint32_t memory_size;
bool has_gmr; bool has_gmr;
bool has_mob; bool has_mob;
......
...@@ -602,7 +602,7 @@ static int vmw_cmd_cid_check(struct vmw_private *dev_priv, ...@@ -602,7 +602,7 @@ static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
{ {
struct vmw_cid_cmd { struct vmw_cid_cmd {
SVGA3dCmdHeader header; SVGA3dCmdHeader header;
__le32 cid; uint32_t cid;
} *cmd; } *cmd;
cmd = container_of(header, struct vmw_cid_cmd, header); cmd = container_of(header, struct vmw_cid_cmd, header);
...@@ -1835,7 +1835,7 @@ static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv, ...@@ -1835,7 +1835,7 @@ static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
return 0; return 0;
} }
static const struct vmw_cmd_entry const vmw_cmd_entries[SVGA_3D_CMD_MAX] = { static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid, VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid,
false, false, false), false, false, false),
VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid, VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid,
...@@ -2032,6 +2032,9 @@ static int vmw_cmd_check(struct vmw_private *dev_priv, ...@@ -2032,6 +2032,9 @@ static int vmw_cmd_check(struct vmw_private *dev_priv,
goto out_invalid; goto out_invalid;
entry = &vmw_cmd_entries[cmd_id]; entry = &vmw_cmd_entries[cmd_id];
if (unlikely(!entry->func))
goto out_invalid;
if (unlikely(!entry->user_allow && !sw_context->kernel)) if (unlikely(!entry->user_allow && !sw_context->kernel))
goto out_privileged; goto out_privileged;
...@@ -2469,7 +2472,7 @@ int vmw_execbuf_process(struct drm_file *file_priv, ...@@ -2469,7 +2472,7 @@ int vmw_execbuf_process(struct drm_file *file_priv,
if (dev_priv->has_mob) { if (dev_priv->has_mob) {
ret = vmw_rebind_contexts(sw_context); ret = vmw_rebind_contexts(sw_context);
if (unlikely(ret != 0)) if (unlikely(ret != 0))
goto out_err; goto out_unlock_binding;
} }
cmd = vmw_fifo_reserve(dev_priv, command_size); cmd = vmw_fifo_reserve(dev_priv, command_size);
......
...@@ -102,6 +102,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data, ...@@ -102,6 +102,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
vmw_fp->gb_aware = true; vmw_fp->gb_aware = true;
param->value = dev_priv->max_mob_pages * PAGE_SIZE; param->value = dev_priv->max_mob_pages * PAGE_SIZE;
break; break;
case DRM_VMW_PARAM_MAX_MOB_SIZE:
param->value = dev_priv->max_mob_size;
break;
default: default:
DRM_ERROR("Illegal vmwgfx get param request: %d\n", DRM_ERROR("Illegal vmwgfx get param request: %d\n",
param->param); param->param);
......
...@@ -371,13 +371,13 @@ int vmw_shader_destroy_ioctl(struct drm_device *dev, void *data, ...@@ -371,13 +371,13 @@ int vmw_shader_destroy_ioctl(struct drm_device *dev, void *data,
TTM_REF_USAGE); TTM_REF_USAGE);
} }
int vmw_shader_alloc(struct vmw_private *dev_priv, static int vmw_shader_alloc(struct vmw_private *dev_priv,
struct vmw_dma_buffer *buffer, struct vmw_dma_buffer *buffer,
size_t shader_size, size_t shader_size,
size_t offset, size_t offset,
SVGA3dShaderType shader_type, SVGA3dShaderType shader_type,
struct ttm_object_file *tfile, struct ttm_object_file *tfile,
u32 *handle) u32 *handle)
{ {
struct vmw_user_shader *ushader; struct vmw_user_shader *ushader;
struct vmw_resource *res, *tmp; struct vmw_resource *res, *tmp;
...@@ -779,6 +779,8 @@ vmw_compat_shader_man_create(struct vmw_private *dev_priv) ...@@ -779,6 +779,8 @@ vmw_compat_shader_man_create(struct vmw_private *dev_priv)
int ret; int ret;
man = kzalloc(sizeof(*man), GFP_KERNEL); man = kzalloc(sizeof(*man), GFP_KERNEL);
if (man == NULL)
return ERR_PTR(-ENOMEM);
man->dev_priv = dev_priv; man->dev_priv = dev_priv;
INIT_LIST_HEAD(&man->list); INIT_LIST_HEAD(&man->list);
......
...@@ -87,6 +87,7 @@ ...@@ -87,6 +87,7 @@
#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
#define DRM_VMW_PARAM_3D_CAPS_SIZE 8 #define DRM_VMW_PARAM_3D_CAPS_SIZE 8
#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
/** /**
* struct drm_vmw_getparam_arg * struct drm_vmw_getparam_arg
......
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