Commit 9859e203 authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Inki Dae

drm/exynos/mixer: fix interrupt clearing

The driver used incorrect flags to clear interrupt status.
The patch fixes it.
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Reviewed-by: default avatarJoonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent e6e771dc
...@@ -718,6 +718,10 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg) ...@@ -718,6 +718,10 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
/* handling VSYNC */ /* handling VSYNC */
if (val & MXR_INT_STATUS_VSYNC) { if (val & MXR_INT_STATUS_VSYNC) {
/* vsync interrupt use different bit for read and clear */
val |= MXR_INT_CLEAR_VSYNC;
val &= ~MXR_INT_STATUS_VSYNC;
/* interlace scan need to check shadow register */ /* interlace scan need to check shadow register */
if (ctx->interlace) { if (ctx->interlace) {
base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
...@@ -743,11 +747,6 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg) ...@@ -743,11 +747,6 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
out: out:
/* clear interrupts */ /* clear interrupts */
if (~val & MXR_INT_EN_VSYNC) {
/* vsync interrupt use different bit for read and clear */
val &= ~MXR_INT_EN_VSYNC;
val |= MXR_INT_CLEAR_VSYNC;
}
mixer_reg_write(res, MXR_INT_STATUS, val); mixer_reg_write(res, MXR_INT_STATUS, val);
spin_unlock(&res->reg_slock); spin_unlock(&res->reg_slock);
......
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