Commit 98e45c16 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Gregory CLEMENT

arm64: dts: marvell: describe the PIC and PMU on Armada 7K/8K

This commit adds the necessary Device Tree description for the PIC
interrupt controller and the PMU available in the Marvell Armada 7K and
Armada 8K SoCs.
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent ec03445c
...@@ -128,6 +128,12 @@ timer { ...@@ -128,6 +128,12 @@ timer {
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
}; };
pmu {
compatible = "arm,cortex-a72-pmu";
interrupt-parent = <&pic>;
interrupts = <17>;
};
odmi: odmi@300000 { odmi: odmi@300000 {
compatible = "marvell,odmi-controller"; compatible = "marvell,odmi-controller";
interrupt-controller; interrupt-controller;
...@@ -140,6 +146,14 @@ odmi: odmi@300000 { ...@@ -140,6 +146,14 @@ odmi: odmi@300000 {
marvell,spi-base = <128>, <136>, <144>, <152>; marvell,spi-base = <128>, <136>, <144>, <152>;
}; };
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
xor@400000 { xor@400000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>, reg = <0x400000 0x1000>,
......
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