Commit 98ea6ad2 authored by Markus Pargmann's avatar Markus Pargmann Committed by Shawn Guo

ARM: dts: imx6: use imx51-ssi

imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online
reconfiguration and needs this for correct interaction with SDMA. This
patch adds imx51-ssi before each imx21-ssi for all imx6 SoCs.
Signed-off-by: default avatarMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent fb06d65c
......@@ -251,7 +251,9 @@ esai: esai@02024000 {
};
ssi1: ssi@02028000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 178>;
......@@ -264,7 +266,9 @@ ssi1: ssi@02028000 {
};
ssi2: ssi@0202c000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 179>;
......@@ -277,7 +281,9 @@ ssi2: ssi@0202c000 {
};
ssi3: ssi@02030000 {
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
compatible = "fsl,imx6q-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 180>;
......
......@@ -225,7 +225,9 @@ uart2: serial@02024000 {
};
ssi1: ssi@02028000 {
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI1>;
......@@ -237,7 +239,9 @@ ssi1: ssi@02028000 {
};
ssi2: ssi@0202c000 {
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI2>;
......@@ -249,7 +253,9 @@ ssi2: ssi@0202c000 {
};
ssi3: ssi@02030000 {
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI3>;
......
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