Commit 98fb2cc1 authored by Rajkumar Manoharan's avatar Rajkumar Manoharan Committed by John W. Linville

ath9k_hw: Update AR9485 initvals to fix system hang issue

This patch fixes system hang when resuming from S3 state
and lower rate sens failure issue.

Cc: stable@kernel.org
Signed-off-by: default avatarRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent e3a4cc2f
...@@ -521,7 +521,7 @@ static const u32 ar9485_1_1_radio_postamble[][2] = { ...@@ -521,7 +521,7 @@ static const u32 ar9485_1_1_radio_postamble[][2] = {
{0x000160ac, 0x24611800}, {0x000160ac, 0x24611800},
{0x000160b0, 0x03284f3e}, {0x000160b0, 0x03284f3e},
{0x0001610c, 0x00170000}, {0x0001610c, 0x00170000},
{0x00016140, 0x10804008}, {0x00016140, 0x50804008},
}; };
static const u32 ar9485_1_1_mac_postamble[][5] = { static const u32 ar9485_1_1_mac_postamble[][5] = {
...@@ -603,7 +603,7 @@ static const u32 ar9485_1_1_radio_core[][2] = { ...@@ -603,7 +603,7 @@ static const u32 ar9485_1_1_radio_core[][2] = {
static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
/* Addr allmodes */ /* Addr allmodes */
{0x00018c00, 0x10052e5e}, {0x00018c00, 0x18052e5e},
{0x00018c04, 0x000801d8}, {0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c}, {0x00018c08, 0x0000080c},
}; };
...@@ -776,7 +776,7 @@ static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = { ...@@ -776,7 +776,7 @@ static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = {
static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = { static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
/* Addr allmodes */ /* Addr allmodes */
{0x00018c00, 0x10013e5e}, {0x00018c00, 0x18013e5e},
{0x00018c04, 0x000801d8}, {0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c}, {0x00018c08, 0x0000080c},
}; };
...@@ -882,7 +882,7 @@ static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = { ...@@ -882,7 +882,7 @@ static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = { static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
/* Addr allmodes */ /* Addr allmodes */
{0x00018c00, 0x10012e5e}, {0x00018c00, 0x18012e5e},
{0x00018c04, 0x000801d8}, {0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c}, {0x00018c08, 0x0000080c},
}; };
...@@ -1021,7 +1021,7 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = { ...@@ -1021,7 +1021,7 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = { static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
/* Addr allmodes */ /* Addr allmodes */
{0x00018c00, 0x10053e5e}, {0x00018c00, 0x18053e5e},
{0x00018c04, 0x000801d8}, {0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c}, {0x00018c08, 0x0000080c},
}; };
......
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