Commit 9a1af5f2 authored by Vladimir Murzin's avatar Vladimir Murzin Committed by Russell King

ARM: 8606/1: V7M: introduce cache operations

This commit implements the cache operation for V7M.

It is based on V7 counterpart and differs as follows:
- cache operations are memory mapped
- only Thumb instruction set is supported
- we don't handle user access faults
Signed-off-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: default avatarAndras Szemzo <sza@esh.hu>
Tested-by: default avatarJoachim Eastwood <manabian@gmail.com>
Tested-by: default avatarAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b2bf482a
This diff is collapsed.
...@@ -7,6 +7,10 @@ ...@@ -7,6 +7,10 @@
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/thread_info.h> #include <asm/thread_info.h>
#ifdef CONFIG_CPU_V7M
#include <asm/v7m.h>
#endif
/* /*
* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
*/ */
...@@ -70,7 +74,13 @@ ...@@ -70,7 +74,13 @@
* on ARMv7. * on ARMv7.
*/ */
.macro dcache_line_size, reg, tmp .macro dcache_line_size, reg, tmp
#ifdef CONFIG_CPU_V7M
movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
ldr \tmp, [\tmp]
#else
mrc p15, 0, \tmp, c0, c0, 1 @ read ctr mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
#endif
lsr \tmp, \tmp, #16 lsr \tmp, \tmp, #16
and \tmp, \tmp, #0xf @ cache line size encoding and \tmp, \tmp, #0xf @ cache line size encoding
mov \reg, #4 @ bytes per word mov \reg, #4 @ bytes per word
...@@ -82,7 +92,13 @@ ...@@ -82,7 +92,13 @@
* on ARMv7. * on ARMv7.
*/ */
.macro icache_line_size, reg, tmp .macro icache_line_size, reg, tmp
#ifdef CONFIG_CPU_V7M
movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
ldr \tmp, [\tmp]
#else
mrc p15, 0, \tmp, c0, c0, 1 @ read ctr mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
#endif
and \tmp, \tmp, #0xf @ cache line size encoding and \tmp, \tmp, #0xf @ cache line size encoding
mov \reg, #4 @ bytes per word mov \reg, #4 @ bytes per word
mov \reg, \reg, lsl \tmp @ actual cache line size mov \reg, \reg, lsl \tmp @ actual cache line size
......
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