Commit 9a5511ea authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo

perf vendor events intel: Update sapphirerapids events/metrics

Update sapphirerapids events to v1.13 improving event
descriptions. Metrics are updated to make TMA info metric names
synchronized. Events and metrics were generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.pyReviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Richter <tmricht@linux.ibm.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230517173805.602113-11-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 98f17fb4
......@@ -23,7 +23,7 @@ GenuineIntel-6-A[AC],v1.01,meteorlake,core
GenuineIntel-6-1[AEF],v3,nehalemep,core
GenuineIntel-6-2E,v3,nehalemex,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-(8F|CF),v1.12,sapphirerapids,core
GenuineIntel-6-(8F|CF),v1.13,sapphirerapids,core
GenuineIntel-6-AF,v1.00,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core
......
......@@ -32,18 +32,20 @@
"UMask": "0x3"
},
{
"BriefDescription": "MEMORY_ACTIVITY.STALLS_L2_MISS",
"BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.",
"CounterMask": "5",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
"PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).",
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "MEMORY_ACTIVITY.STALLS_L3_MISS",
"BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.",
"CounterMask": "9",
"EventCode": "0x47",
"EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
"PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).",
"SampleAfterValue": "1000003",
"UMask": "0x9"
},
......
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......@@ -464,7 +464,7 @@
"Unit": "M2M"
},
{
"BriefDescription": "Counts the time when FM didn? do d2c for fill reads (cross tile case)",
"BriefDescription": "Counts the time when FM didn't do d2c for fill reads (cross tile case)",
"EventCode": "0x4a",
"EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
"PerPkg": "1",
......
......@@ -2480,11 +2480,11 @@
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to (?)",
"BriefDescription": "DRAM Precharge commands",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
"PublicDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.",
"PublicDescription": "DRAM Precharge commands. Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x88",
"Unit": "iMC"
},
......@@ -3236,7 +3236,7 @@
"Unit": "iMC"
},
{
"BriefDescription": "2LM Tag check hit due to memory read (bug?)",
"BriefDescription": "2LM Tag check hit due to memory read",
"EventCode": "0xd3",
"EventName": "UNC_M_TAGCHK.NM_RD_HIT",
"PerPkg": "1",
......@@ -3244,7 +3244,7 @@
"Unit": "iMC"
},
{
"BriefDescription": "2LM Tag check hit due to memory write (bug?)",
"BriefDescription": "2LM Tag check hit due to memory write",
"EventCode": "0xd3",
"EventName": "UNC_M_TAGCHK.NM_WR_HIT",
"PerPkg": "1",
......
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