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Merge tag 'qcom-pinctrl-6.2-2' of... 

Merge tag 'qcom-pinctrl-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel

Qualcomm pinctrl Devicetree bindings changes for v6.2, part two

Continuation of refactoring and improving Qualcomm pin controller bindings:
1. Narrow compatible combinations in PMIC MPP.
2. Convert several bindings from TXT to DT schema format: QCS404,
   IPQ8074, MSM8660, MSM8916, MSM8960 and MSM8976.
parents 29c10bce 86bfee31
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Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt deleted 100644 → 0
View file @ 29c10bce
Qualcomm Technologies, Inc. IPQ8074 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
IPQ8074 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,ipq8074-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio69
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
atest_char, atest_char0, atest_char1, atest_char2,
atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1,
cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en,
ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0,
mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc,
mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk,
pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync,
pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1,
pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b,
qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a,
wci2b, wci2c, wci2d
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 70>;
interrupt-controller;
#interrupt-cells = <2>;
uart2: uart2-default {
mux {
pins = "gpio23", "gpio24";
function = "blsp4_uart1";
};
rx {
pins = "gpio23";
drive-strength = <4>;
bias-disable;
};
tx {
pins = "gpio24";
drive-strength = <2>;
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml 0 → 100644
View file @ 9aad5769
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm IPQ8074 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.
properties:
compatible:
const: qcom,ipq8074-pinctrl
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
gpio-reserved-ranges:
minItems: 1
maxItems: 35
gpio-line-names:
maxItems: 70
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq8074-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq8074-tlmm-state"
additionalProperties: false
$defs:
qcom-ipq8074-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-6][0-9]|70)$"
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0,
cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0,
led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2,
mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,
pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx,
pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0,
pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write,
tsens_max, wci2a, wci2b, wci2c, wci2d ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <0x2>;
gpio-ranges = <&tlmm 0 0 70>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <0x2>;
serial4-state {
pins = "gpio23", "gpio24";
function = "blsp4_uart1";
drive-strength = <8>;
bias-disable;
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt deleted 100644 → 0
View file @ 29c10bce
Qualcomm MSM8660 TLMM block
Required properties:
- compatible: "qcom,msm8660-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
output-low, output-high.
Non-empty subnodes must specify the 'pins' property.
Valid values for pins are:
gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data
Valid values for function are:
gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b,
gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n,
gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n,
gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s,
lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1,
usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs
Example:
msmgpio: pinctrl@800000 {
compatible = "qcom,msm8660-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 173>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&gsbi12_uart>;
gsbi12_uart: gsbi12-uart {
mux {
pins = "gpio117", "gpio118";
function = "gsbi12";
};
tx {
pins = "gpio118";
drive-strength = <8>;
bias-disable;
};
rx {
pins = "gpio117";
drive-strength = <2>;
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml 0 → 100644
View file @ 9aad5769
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8660-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8660 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC.
properties:
compatible:
const: qcom,msm8660-pinctrl
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
gpio-reserved-ranges:
minItems: 1
maxItems: 86
gpio-line-names:
maxItems: 173
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-msm8660-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-msm8660-tlmm-state"
additionalProperties: false
$defs:
qcom-msm8660-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-2])$"
- enum: [ sdc3_clk, sdc3_cmd, sdc3_data, sdc4_clk, sdc4_cmd, sdc4_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a,
gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n,
gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2,
gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, gsbi2_spi_cs3_n, gsbi3,
gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4,
gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12,
hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2,
sdc5, tsif1, tsif2, usb_fs1, usb_fs1_oe_n, usb_fs2,
usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@800000 {
compatible = "qcom,msm8660-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 173>;
#gpio-cells = <2>;
interrupts = <0 16 0x4>;
interrupt-controller;
#interrupt-cells = <2>;
gsbi3-i2c-state {
pins = "gpio43", "gpio44";
function = "gsbi3";
drive-strength = <8>;
bias-disable;
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt deleted 100644 → 0
View file @ 29c10bce
Qualcomm MSM8916 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8916 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,msm8916-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio121,
sdc1_clk,
sdc1_cmd,
sdc1_data
sdc2_clk,
sdc2_cmd,
sdc2_data,
qdsd_cmd,
qdsd_data0,
qdsd_data1,
qdsd_data2,
qdsd_data3
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0,
atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en,
bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2,
blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3,
blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4,
blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2,
cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c,
cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out,
display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us,
ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, gsm0_tx1,
gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, ldo_en,
ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, nav_pps, nav_tsync,
pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc,
pwr_crypto_enabled_a, pwr_crypto_enabled_b, pwr_modem_enabled_a,
pwr_modem_enabled_b, pwr_nav_enabled_a, pwr_nav_enabled_b,
qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, qdss_ctitrig_in_b0,
qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, qdss_ctitrig_out_a1,
qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, qdss_traceclk_a,
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
qdss_tracedata_b, reset_n, sd_card, sd_write, sec_mi2s, smb_int,
ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm,
wcss_wlan, webcam1_rst
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 122>;
interrupt-controller;
#interrupt-cells = <2>;
uart2: uart2-default {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
};
tx {
pins = "gpio4";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml 0 → 100644
View file @ 9aad5769
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8916-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8916 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm MSM8916 SoC.
properties:
compatible:
const: qcom,msm8916-pinctrl
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
gpio-reserved-ranges:
minItems: 1
maxItems: 61
gpio-line-names:
maxItems: 122
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-msm8916-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-msm8916-tlmm-state"
additionalProperties: false
$defs:
qcom-msm8916-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[01])$"
- enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char,
atest_char0, atest_char1, atest_char2, atest_char3,
atest_combodac, atest_gpsadc0, atest_gpsadc1, atest_tsens,
atest_wlan0, atest_wlan1, backlight_en, bimc_dte0, bimc_dte1,
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2,
blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2,
blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_uart1,
blsp_uart2, blsp_uim1, blsp_uim2, cam1_rst, cam1_standby,
cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0,
cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out,
display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc,
euro_us, ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b,
gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b,
gsm0_tx0, gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0,
kpsns1, kpsns2, ldo_en, ldo_update, mag_int, mdp_vsync,
modem_tsync, m_voc, nav_pps, nav_tsync, pa_indicator, pbs0,
pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc,
pwr_crypto_enabled_a, pwr_crypto_enabled_b,
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1,
qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0,
qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1,
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, reset_n,
sd_card, sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1,
uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan,
webcam1_rst ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
msmgpio: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 122>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1-uart2-sleep-state {
pins = "gpio4", "gpio5";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
spi1-default-state {
spi-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
cs-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt deleted 100644 → 0
View file @ 29c10bce
Qualcomm MSM8960 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8960 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,msm8960-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio151,
sdc1_clk,
sdc1_cmd,
sdc1_data
sdc3_clk,
sdc3_cmd,
sdc3_data
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2,
codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking,
gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a,
gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a,
gp_pdm_0b, gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gpio,
gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n,
gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l,
gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l,
gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10,
gsbi11, gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n,
gsbi11_spi_cs2a_n, gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n,
gsbi12, hdmi_cec, hdmi_ddc_clock, hdmi_ddc_data,
hdmi_hot_plug_detect, hsic, mdp_vsync, mi2s, mic_i2s,
pmb_clk, pmb_ext_ctrl, ps_hold, rpm_wdog, sdc2, sdc4, sdc5,
slimbus1, slimbus2, spkr_i2s, ssbi1, ssbi2, ssbi_ext_gps,
ssbi_pmic2, ssbi_qpa1, ssbi_ts, tsif1, tsif2, ts_eoc,
usb_fs1, usb_fs1_oe, usb_fs1_oe_n, usb_fs2, usb_fs2_oe,
usb_fs2_oe_n, vfe_camif_timer1_a, vfe_camif_timer1_b,
vfe_camif_timer2, vfe_camif_timer3_a, vfe_camif_timer3_b,
vfe_camif_timer4_a, vfe_camif_timer4_b, vfe_camif_timer4_c,
vfe_camif_timer5_a, vfe_camif_timer5_b, vfe_camif_timer6_a,
vfe_camif_timer6_b, vfe_camif_timer6_c, vfe_camif_timer7_a,
vfe_camif_timer7_b, vfe_camif_timer7_c, wlan
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
msmgpio: pinctrl@800000 {
compatible = "qcom,msm8960-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 152>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;
gsbi8_uart: gsbi8-uart {
mux {
pins = "gpio34", "gpio35";
function = "gsbi8";
};
tx {
pins = "gpio34";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio35";
drive-strength = <2>;
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml 0 → 100644
View file @ 9aad5769
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8960-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8960 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm MSM8960 SoC.
properties:
compatible:
const: qcom,msm8960-pinctrl
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
gpio-reserved-ranges:
minItems: 1
maxItems: 76
gpio-line-names:
maxItems: 152
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-msm8960-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-msm8960-tlmm-state"
additionalProperties: false
$defs:
qcom-msm8960-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-1])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd,
sdc3_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2,
codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking,
gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a,
gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a, gp_pdm_0b,
gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gsbi1,
gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n,
gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l,
gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l,
gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11,
gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n, gsbi11_spi_cs2a_n,
gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n, gsbi12, hdmi_cec,
hdmi_ddc_clock, hdmi_ddc_data, hdmi_hot_plug_detect, hsic,
mdp_vsync, mi2s, mic_i2s, pmb_clk, pmb_ext_ctrl, ps_hold,
rpm_wdog, sdc2, sdc4, sdc5, slimbus1, slimbus2, spkr_i2s,
ssbi1, ssbi2, ssbi_ext_gps, ssbi_pmic2, ssbi_qpa1, ssbi_ts,
tsif1, tsif2, ts_eoc, usb_fs1, usb_fs1_oe, usb_fs1_oe_n,
usb_fs2, usb_fs2_oe, usb_fs2_oe_n, vfe_camif_timer1_a,
vfe_camif_timer1_b, vfe_camif_timer2, vfe_camif_timer3_a,
vfe_camif_timer3_b, vfe_camif_timer4_a, vfe_camif_timer4_b,
vfe_camif_timer4_c, vfe_camif_timer5_a, vfe_camif_timer5_b,
vfe_camif_timer6_a, vfe_camif_timer6_b, vfe_camif_timer6_c,
vfe_camif_timer7_a, vfe_camif_timer7_b, vfe_camif_timer7_c,
wlan ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
msmgpio: pinctrl@800000 {
compatible = "qcom,msm8960-pinctrl";
reg = <0x800000 0x4000>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 152>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
spi1-default-state {
mosi-pins {
pins = "gpio6";
function = "gsbi1";
drive-strength = <12>;
bias-disable;
};
miso-pins {
pins = "gpio7";
function = "gsbi1";
drive-strength = <12>;
bias-disable;
};
cs-pins {
pins = "gpio8";
function = "gpio";
drive-strength = <12>;
bias-disable;
output-low;
};
clk-pins {
pins = "gpio9";
function = "gsbi1";
drive-strength = <12>;
bias-disable;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.txt deleted 100644 → 0
View file @ 29c10bce
Qualcomm MSM8976 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8956 and MSM8976 platforms.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,msm8976-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio145
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data,
sdc2_clk, sdc2_cmd, sdc2_data,
sdc3_clk, sdc3_cmd, sdc3_data
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2,
blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3,
qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b,
blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5,
qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a,
qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b,
blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a,
sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi,
blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a,
uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset,
uim1_present, uim2_data, uim2_clk, uim2_reset,
uim2_present, ts_xvdd, mipi_dsi0, us_euro, ts_resout,
ts_sample, sec_mi2s_mclk_b, pri_mi2s, codec_reset,
cdc_pdm0, us_emitter, pri_mi2s_mclk_b, pri_mi2s_mclk_c,
lpass_slimbus, lpass_slimbus0, lpass_slimbus1, codec_int1,
codec_int2, wcss_bt, sdc3, wcss_wlan2, wcss_wlan1,
wcss_wlan0, wcss_wlan, wcss_fm, key_volp, key_snapshot,
key_focus, key_home, pwr_down, dmic0_clk, hdmi_int,
dmic0_data, wsa_vi, wsa_en, blsp_spi8, wsa_irq, blsp_i2c8,
pa_indicator, modem_tsync, ssbi_wtr1, gsm1_tx, gsm0_tx,
sdcard_det, sec_mi2s, ss_switch,
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,msm8976-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 145>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1_uart2_active: blsp1_uart2_active {
mux {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "blsp_uart2";
};
config {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml 0 → 100644
View file @ 9aad5769
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8976-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8976 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm MSM8976 SoC.
properties:
compatible:
const: qcom,msm8976-pinctrl
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
gpio-reserved-ranges:
minItems: 1
maxItems: 73
gpio-line-names:
maxItems: 145
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-msm8976-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-msm8976-tlmm-state"
additionalProperties: false
$defs:
qcom-msm8976-tlmm-state:
type: object
description:
Desired pin configuration for a device or its specific state (like sleep
or active).
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
description:
List of gpio pins affected by the properties specified in this state.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-4])$"
- enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk,
sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2,
blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3,
qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b,
blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5,
qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a,
qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b,
blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a,
sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi,
blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a,
uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset,
uim1_present, uim2_data, uim2_clk, uim2_reset, uim2_present,
ts_xvdd, mipi_dsi0, us_euro, ts_resout, ts_sample,
sec_mi2s_mclk_b, pri_mi2s, codec_reset, cdc_pdm0, us_emitter,
pri_mi2s_mclk_b, pri_mi2s_mclk_c, lpass_slimbus,
lpass_slimbus0, lpass_slimbus1, codec_int1, codec_int2,
wcss_bt, sdc3, wcss_wlan2, wcss_wlan1, wcss_wlan0, wcss_wlan,
wcss_fm, key_volp, key_snapshot, key_focus, key_home, pwr_down,
dmic0_clk, hdmi_int, dmic0_data, wsa_vi, wsa_en, blsp_spi8,
wsa_irq, blsp_i2c8, pa_indicator, modem_tsync, ssbi_wtr1,
gsm1_tx, gsm0_tx, sdcard_det, sec_mi2s, ss_switch ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,msm8976-pinctrl";
reg = <0x1000000 0x300000>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 145>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1-uart2-active-state {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "blsp_uart2";
drive-strength = <2>;
bias-disable;
};
};
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
View file @ 9aad5769
......@@ -15,28 +15,29 @@ description:
properties:
compatible:
items:
- enum:
- qcom,pm8018-mpp
- qcom,pm8019-mpp
- qcom,pm8038-mpp
- qcom,pm8058-mpp
- qcom,pm8226-mpp
- qcom,pm8821-mpp
- qcom,pm8841-mpp
- qcom,pm8916-mpp
- qcom,pm8917-mpp
- qcom,pm8921-mpp
- qcom,pm8941-mpp
- qcom,pm8950-mpp
- qcom,pmi8950-mpp
- qcom,pm8994-mpp
- qcom,pma8084-mpp
- qcom,pmi8994-mpp
- enum:
- qcom,spmi-mpp
- qcom,ssbi-mpp
oneOf:
- items:
- enum:
- qcom,pm8019-mpp
- qcom,pm8226-mpp
- qcom,pm8841-mpp
- qcom,pm8916-mpp
- qcom,pm8941-mpp
- qcom,pm8950-mpp
- qcom,pmi8950-mpp
- qcom,pm8994-mpp
- qcom,pma8084-mpp
- qcom,pmi8994-mpp
- const: qcom,spmi-mpp
- items:
- enum:
- qcom,pm8018-mpp
- qcom,pm8038-mpp
- qcom,pm8058-mpp
- qcom,pm8821-mpp
- qcom,pm8917-mpp
- qcom,pm8921-mpp
- const: qcom,ssbi-mpp
reg:
maxItems: 1
......
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt deleted 100644 → 0
View file @ 29c10bce
Qualcomm QCS404 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
QCS404 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,qcs404-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the north, south and east TLMM
tiles.
- reg-names:
Usage: required
Value type: <stringlist>
Defintiion: names for the cells of reg, must contain "north", "south"
and "east".
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio119
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data
Supports bias and drive-strength
ufs_reset
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
gpio, hdmi_tx, hdmi_ddc, blsp_uart_tx_a2, blsp_spi2, m_voc,
qdss_cti_trig_in_a0, blsp_uart_rx_a2, qdss_tracectl_a,
blsp_uart2, aud_cdc, blsp_i2c_sda_a2, qdss_tracedata_a,
blsp_i2c_scl_a2, qdss_tracectl_b, qdss_cti_trig_in_b0,
blsp_uart1, blsp_spi_mosi_a1, blsp_spi_miso_a1,
qdss_tracedata_b, blsp_i2c1, blsp_spi_cs_n_a1, gcc_plltest,
blsp_spi_clk_a1, rgb_data0, blsp_uart5, blsp_spi5,
adsp_ext, rgb_data1, prng_rosc, rgb_data2, blsp_i2c5,
gcc_gp1_clk_b, rgb_data3, gcc_gp2_clk_b, blsp_spi0,
blsp_uart0, gcc_gp3_clk_b, blsp_i2c0, qdss_traceclk_b,
pcie_clk, nfc_irq, blsp_spi4, nfc_dwl, audio_ts, rgb_data4,
spi_lcd, blsp_uart_tx_b2, gcc_gp3_clk_a, rgb_data5,
blsp_uart_rx_b2, blsp_i2c_sda_b2, blsp_i2c_scl_b2,
pwm_led11, i2s_3_data0_a, ebi2_lcd, i2s_3_data1_a,
i2s_3_data2_a, atest_char, pwm_led3, i2s_3_data3_a,
pwm_led4, i2s_4, ebi2_a, dsd_clk_b, pwm_led5, pwm_led6,
pwm_led7, pwm_led8, pwm_led24, spkr_dac0, blsp_i2c4,
pwm_led9, pwm_led10, spdifrx_opt, pwm_led12, pwm_led13,
pwm_led14, wlan1_adc1, rgb_data_b0, pwm_led15,
blsp_spi_mosi_b1, wlan1_adc0, rgb_data_b1, pwm_led16,
blsp_spi_miso_b1, qdss_cti_trig_out_b0, wlan2_adc1,
rgb_data_b2, pwm_led17, blsp_spi_cs_n_b1, wlan2_adc0,
rgb_data_b3, pwm_led18, blsp_spi_clk_b1, rgb_data_b4,
pwm_led19, ext_mclk1_b, qdss_traceclk_a, rgb_data_b5,
pwm_led20, atest_char3, i2s_3_sck_b, ldo_update, bimc_dte0,
rgb_hsync, pwm_led21, i2s_3_ws_b, dbg_out, rgb_vsync,
i2s_3_data0_b, ldo_en, hdmi_dtest, rgb_de, i2s_3_data1_b,
hdmi_lbk9, rgb_clk, atest_char1, i2s_3_data2_b, ebi_cdc,
hdmi_lbk8, rgb_mdp, atest_char0, i2s_3_data3_b, hdmi_lbk7,
rgb_data_b6, rgb_data_b7, hdmi_lbk6, rgmii_int, cri_trng1,
rgmii_wol, cri_trng0, gcc_tlmm, rgmii_ck, rgmii_tx,
hdmi_lbk5, hdmi_pixel, hdmi_rcv, hdmi_lbk4, rgmii_ctl,
ext_lpass, rgmii_rx, cri_trng, hdmi_lbk3, hdmi_lbk2,
qdss_cti_trig_out_b1, rgmii_mdio, hdmi_lbk1, rgmii_mdc,
hdmi_lbk0, ir_in, wsa_en, rgb_data6, rgb_data7,
atest_char2, ebi_ch0, blsp_uart3, blsp_spi3, sd_write,
blsp_i2c3, gcc_gp1_clk_a, qdss_cti_trig_in_b1,
gcc_gp2_clk_a, ext_mclk0, mclk_in1, i2s_1, dsd_clk_a,
qdss_cti_trig_in_a1, rgmi_dll1, pwm_led22, pwm_led23,
qdss_cti_trig_out_a0, rgmi_dll2, pwm_led1,
qdss_cti_trig_out_a1, pwm_led2, i2s_2, pll_bist,
ext_mclk1_a, mclk_in2, bimc_dte1, i2s_3_sck_a, i2s_3_ws_a
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,qcs404-pinctrl";
reg = <0x01000000 0x200000>,
<0x01300000 0x200000>,
<0x07b00000 0x200000>;
reg-names = "south", "north", "east";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 120>;
interrupt-controller;
#interrupt-cells = <2>;
};
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml 0 → 100644
View file @ 9aad5769
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,qcs404-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QCS404 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm QCS404 SoC.
properties:
compatible:
const: qcom,qcs404-pinctrl
reg:
maxItems: 3
reg-names:
items:
- const: south
- const: north
- const: east
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
gpio-reserved-ranges:
minItems: 1
maxItems: 60
gpio-line-names:
maxItems: 120
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-qcs404-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-qcs404-tlmm-state"
additionalProperties: false
$defs:
qcom-qcs404-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, adsp_ext, atest_char, atest_char0, atest_char1,
atest_char2, atest_char3, aud_cdc, audio_ts, bimc_dte0,
bimc_dte1, blsp_i2c0, blsp_i2c1, blsp_i2c3, blsp_i2c4,
blsp_i2c5, blsp_i2c_scl_a2, blsp_i2c_scl_b2, blsp_i2c_sda_a2,
blsp_i2c_sda_b2, blsp_spi0, blsp_spi2, blsp_spi3, blsp_spi4,
blsp_spi5, blsp_spi_clk_a1, blsp_spi_clk_b1, blsp_spi_cs_n_a1,
blsp_spi_cs_n_b1, blsp_spi_miso_a1, blsp_spi_miso_b1,
blsp_spi_mosi_a1, blsp_spi_mosi_b1, blsp_uart0, blsp_uart1,
blsp_uart2, blsp_uart3, blsp_uart5, blsp_uart_rx_a2,
blsp_uart_rx_b2, blsp_uart_tx_a2, blsp_uart_tx_b2, cri_trng,
cri_trng0, cri_trng1, dbg_out, dsd_clk_a, dsd_clk_b, ebi2_a,
ebi2_lcd, ebi_cdc, ebi_ch0, ext_lpass, ext_mclk0, ext_mclk1_a,
ext_mclk1_b, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest,
gcc_tlmm, hdmi_ddc, hdmi_dtest, hdmi_lbk0, hdmi_lbk1,
hdmi_lbk2, hdmi_lbk3, hdmi_lbk4, hdmi_lbk5, hdmi_lbk6,
hdmi_lbk7, hdmi_lbk8, hdmi_lbk9, hdmi_pixel, hdmi_rcv, hdmi_tx,
i2s_1, i2s_2, i2s_3_data0_a, i2s_3_data0_b, i2s_3_data1_a,
i2s_3_data1_b, i2s_3_data2_a, i2s_3_data2_b, i2s_3_data3_a,
i2s_3_data3_b, i2s_3_sck_a, i2s_3_sck_b, i2s_3_ws_a,
i2s_3_ws_b, i2s_4, ir_in, ldo_en, ldo_update, mclk_in1,
mclk_in2, m_voc, nfc_dwl, nfc_irq, pcie_clk, pll_bist,
prng_rosc, pwm_led1, pwm_led10, pwm_led11, pwm_led12,
pwm_led13, pwm_led14, pwm_led15, pwm_led16, pwm_led17,
pwm_led18, pwm_led19, pwm_led2, pwm_led20, pwm_led21,
pwm_led22, pwm_led23, pwm_led24, pwm_led3, pwm_led4, pwm_led5,
pwm_led6, pwm_led7, pwm_led8, pwm_led9, qdss_cti_trig_in_a0,
qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
qdss_tracedata_a, qdss_tracedata_b, rgb_clk, rgb_data0,
rgb_data1, rgb_data2, rgb_data3, rgb_data4, rgb_data5,
rgb_data6, rgb_data7, rgb_data_b0, rgb_data_b1, rgb_data_b2,
rgb_data_b3, rgb_data_b4, rgb_data_b5, rgb_data_b6,
rgb_data_b7, rgb_de, rgb_hsync, rgb_mdp, rgb_vsync, rgmi_dll1,
rgmi_dll2, rgmii_ck, rgmii_ctl, rgmii_int, rgmii_mdc,
rgmii_mdio, rgmii_rx, rgmii_tx, rgmii_wol, sd_write,
spdifrx_opt, spi_lcd, spkr_dac0, wlan1_adc0, wlan1_adc1,
wlan2_adc0, wlan2_adc1, wsa_en ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,qcs404-pinctrl";
reg = <0x01000000 0x200000>,
<0x01300000 0x200000>,
<0x07b00000 0x200000>;
reg-names = "south", "north", "east";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 120>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1-i2c1-default-state {
pins = "gpio24", "gpio25";
function = "blsp_i2c1";
};
blsp1-i2c2-default-state {
sda-pins {
pins = "gpio19";
function = "blsp_i2c_sda_a2";
};
scl-pins {
pins = "gpio20";
function = "blsp_i2c_scl_a2";
};
};
};
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