Commit 9ad95c46 authored by Will Deacon's avatar Will Deacon

Merge branch 'perf/updates' into aarch64/for-next/core

Merge in arm64 perf updates:

  * xgene system PMUv3 support
  * 16-bit events for ARMv8.1
parents bcde519e c0f7f7ac
......@@ -552,7 +552,7 @@ static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
return 0;
}
static struct of_device_id armv6_pmu_of_device_ids[] = {
static const struct of_device_id armv6_pmu_of_device_ids[] = {
{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
{.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
{.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
......
......@@ -529,7 +529,7 @@ static struct attribute_group armv8_pmuv3_events_attr_group = {
.is_visible = armv8pmu_event_attr_is_visible,
};
PMU_FORMAT_ATTR(event, "config:0-9");
PMU_FORMAT_ATTR(event, "config:0-15");
static struct attribute *armv8_pmuv3_format_attrs[] = {
&format_attr_event.attr,
......
......@@ -3,9 +3,10 @@
#
menu "Performance monitor support"
depends on PERF_EVENTS
config ARM_PMU
depends on PERF_EVENTS && (ARM || ARM64)
depends on ARM || ARM64
bool "ARM PMU framework"
default y
help
......@@ -18,7 +19,7 @@ config ARM_PMU_ACPI
config QCOM_L2_PMU
bool "Qualcomm Technologies L2-cache PMU"
depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI
depends on ARCH_QCOM && ARM64 && ACPI
help
Provides support for the L2 cache performance monitor unit (PMU)
in Qualcomm Technologies processors.
......@@ -27,7 +28,7 @@ config QCOM_L2_PMU
config QCOM_L3_PMU
bool "Qualcomm Technologies L3-cache PMU"
depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI
depends on ARCH_QCOM && ARM64 && ACPI
select QCOM_IRQ_COMBINER
help
Provides support for the L3 cache performance monitor unit (PMU)
......@@ -36,7 +37,7 @@ config QCOM_L3_PMU
monitoring L3 cache events.
config XGENE_PMU
depends on PERF_EVENTS && ARCH_XGENE
depends on ARCH_XGENE
bool "APM X-Gene SoC PMU"
default n
help
......
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