drm/amd/display: Varibright fix bug and review comments

Fix bug and make changes from review 132656
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc.c

@@ -1363,11 +1363,15 @@ static void commit_planes_for_stream(struct dc *dc,
 			dc->hwss.apply_ctx_for_surface(
 					dc, pipe_ctx->stream, stream_status->plane_count, context);
 
-			if (stream_update->abm_setting.stream_update) {
-				if (dc->res_pool->abm)
-					dc->res_pool->abm->funcs->set_abm_level(
-							dc->res_pool->abm, stream->abm_settings.abm_level);
-				stream->abm_settings.stream_update = 0;
+			if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
+				if (pipe_ctx->stream_res.tg->funcs->is_blanked) {
+					// if otg funcs defined check if blanked before programming
+					if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
+						pipe_ctx->stream_res.abm->funcs->set_abm_level(
+								pipe_ctx->stream_res.abm, stream->abm_level);
+				} else
+					pipe_ctx->stream_res.abm->funcs->set_abm_level(
+							pipe_ctx->stream_res.abm, stream->abm_level);
 			}
 		}
 	}

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

@@ -1124,6 +1124,7 @@ bool dc_add_plane_to_context(
 		ASSERT(tail_pipe);
 
 		free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
+		free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
 		free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
 		free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
 		free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
@@ -1736,6 +1737,10 @@ enum dc_status resource_map_pool_resources(
 					   pipe_ctx->stream_res.audio, true);
 	}
 
+	/* Add ABM to the resource if on EDP */
+	if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
+		pipe_ctx->stream_res.abm = pool->abm;
+
 	for (i = 0; i < context->stream_count; i++)
 		if (context->streams[i] == stream) {
 			context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dc.h

@@ -60,11 +60,6 @@ struct dc_versions {
 	struct dmcu_version dmcu_version;
 };
 
-struct abm_setting {
-	bool stream_update;
-	unsigned int abm_level;
-};
-
 struct dc_caps {
 	uint32_t max_streams;
 	uint32_t max_links;

drivers/gpu/drm/amd/display/dc/dc_stream.h

@@ -75,7 +75,7 @@ struct dc_stream_state {
 	/* TODO: CEA VIC */
 
 	/* DMCU info */
-	struct abm_setting abm_settings;
+	unsigned int abm_level;
 
 	/* from core_stream struct */
 	struct dc_context *ctx;
@@ -109,7 +109,7 @@ struct dc_stream_update {
 	struct dc_transfer_func *out_transfer_func;
 	struct dc_hdr_static_metadata *hdr_static_metadata;
 	enum color_transfer_func color_output_tf;
-	struct abm_setting abm_setting;
+	unsigned int *abm_level;
 };
 
 bool dc_is_stream_unchanged(

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

@@ -1781,20 +1781,31 @@ static void update_dchubp_dpp(
 }
 
 static void dcn10_otg_blank(
+		struct dc *dc,
 		struct stream_resource stream_res,
-		struct abm *abm,
 		struct dc_stream_state *stream,
 		bool blank)
 {
+	enum dc_color_space color_space;
+	struct tg_color black_color = {0};
+
+	/* program otg blank color */
+	color_space = stream->output_color_space;
+	color_space_to_black_color(dc, color_space, &black_color);
+
+	if (stream_res.tg->funcs->set_blank_color)
+		stream_res.tg->funcs->set_blank_color(
+				stream_res.tg,
+				&black_color);
 
 	if (!blank) {
 		if (stream_res.tg->funcs->set_blank)
 			stream_res.tg->funcs->set_blank(stream_res.tg, blank);
-		if (abm)
-			abm->funcs->set_abm_level(abm, stream->abm_settings.abm_level);
+		if (stream_res.abm)
+			stream_res.abm->funcs->set_abm_level(stream_res.abm, stream->abm_level);
 	} else if (blank) {
-		if (abm)
-			abm->funcs->set_abm_immediate_disable(abm);
+		if (stream_res.abm)
+			stream_res.abm->funcs->set_abm_immediate_disable(stream_res.abm);
 		if (stream_res.tg->funcs->set_blank)
 			stream_res.tg->funcs->set_blank(stream_res.tg, blank);
 	}
@@ -1817,7 +1828,7 @@ static void program_all_pipe_in_tree(
 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
 				pipe_ctx->stream_res.tg);
 
-		dcn10_otg_blank(pipe_ctx->stream_res, dc->res_pool->abm,
+		dcn10_otg_blank(dc, pipe_ctx->stream_res,
 				pipe_ctx->stream, blank);
 	}
 
@@ -1941,7 +1952,7 @@ static void dcn10_apply_ctx_for_surface(
 
 	if (num_planes == 0) {
 		/* OTG blank before remove all front end */
-		dcn10_otg_blank(top_pipe_to_program->stream_res, dc->res_pool->abm, top_pipe_to_program->stream, true);
+		dcn10_otg_blank(dc, top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);
 	}
 
 	/* Disconnect unused mpcc */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -963,6 +963,7 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
 
 	idle_pipe->stream = head_pipe->stream;
 	idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
+	idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
 	idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
 
 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

@@ -194,6 +194,8 @@ struct stream_resource {
 
 	struct pixel_clk_params pix_clk_params;
 	struct encoder_info_frame encoder_info_frame;
+
+	struct abm *abm;
 };
 
 struct plane_resource {