Commit 9aef809b authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/powerplay: expose supported clock domains only through sysfs

Do not expose those unsupported clock domains through sysfs on
Arcturus.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d80ead63
...@@ -2828,10 +2828,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) ...@@ -2828,10 +2828,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
DRM_ERROR("failed to create device file pp_dpm_socclk\n"); DRM_ERROR("failed to create device file pp_dpm_socclk\n");
return ret; return ret;
} }
ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk); if (adev->asic_type != CHIP_ARCTURUS) {
if (ret) { ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
DRM_ERROR("failed to create device file pp_dpm_dcefclk\n"); if (ret) {
return ret; DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
return ret;
}
} }
} }
if (adev->asic_type >= CHIP_VEGA20) { if (adev->asic_type >= CHIP_VEGA20) {
...@@ -2841,10 +2843,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) ...@@ -2841,10 +2843,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
return ret; return ret;
} }
} }
ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie); if (adev->asic_type != CHIP_ARCTURUS) {
if (ret) { ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
DRM_ERROR("failed to create device file pp_dpm_pcie\n"); if (ret) {
return ret; DRM_ERROR("failed to create device file pp_dpm_pcie\n");
return ret;
}
} }
ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od); ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
if (ret) { if (ret) {
...@@ -2948,9 +2952,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) ...@@ -2948,9 +2952,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk); device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
if (adev->asic_type >= CHIP_VEGA10) { if (adev->asic_type >= CHIP_VEGA10) {
device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk); device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk); if (adev->asic_type != CHIP_ARCTURUS)
device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
} }
device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie); if (adev->asic_type != CHIP_ARCTURUS)
device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
if (adev->asic_type >= CHIP_VEGA20) if (adev->asic_type >= CHIP_VEGA20)
device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk); device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
device_remove_file(adev->dev, &dev_attr_pp_sclk_od); device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
......
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