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Commit 9b096283 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/disp/nv50-: simplify definiton of core channels 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 6d41a753
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Showing with 91 additions and 428 deletions
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
View file @ 9b096283
......@@ -79,14 +79,8 @@ nvkm-y += nvkm/engine/disp/basegp102.o
nvkm-y += nvkm/engine/disp/corenv50.o
nvkm-y += nvkm/engine/disp/coreg84.o
nvkm-y += nvkm/engine/disp/coreg94.o
nvkm-y += nvkm/engine/disp/coregt200.o
nvkm-y += nvkm/engine/disp/coregt215.o
nvkm-y += nvkm/engine/disp/coregf119.o
nvkm-y += nvkm/engine/disp/coregk104.o
nvkm-y += nvkm/engine/disp/coregk110.o
nvkm-y += nvkm/engine/disp/coregm107.o
nvkm-y += nvkm/engine/disp/coregm200.o
nvkm-y += nvkm/engine/disp/coregp100.o
nvkm-y += nvkm/engine/disp/coregp102.o
nvkm-y += nvkm/engine/disp/ovlynv50.o
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
View file @ 9b096283
......@@ -63,6 +63,11 @@ int nv50_disp_base_new_(const struct nv50_disp_dmac_func *,
struct nv50_disp *, int chid,
const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_core_new_(const struct nv50_disp_dmac_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp *, int chid,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp *, int chid,
......@@ -75,14 +80,21 @@ int nv50_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int nv50_disp_base_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int nv50_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int nv50_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int g84_disp_base_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int g84_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int g84_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int g94_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gt200_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
......@@ -92,9 +104,13 @@ int gf119_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gf119_disp_base_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gf119_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gf119_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gk104_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gk104_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
......@@ -104,6 +120,8 @@ int gp102_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gp102_disp_base_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gp102_disp_core_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gp102_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
......@@ -135,11 +153,11 @@ extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
extern const struct nv50_disp_chan_mthd g84_disp_core_chan_mthd;
extern const struct nv50_disp_chan_mthd g84_disp_core_mthd;
extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac;
extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head;
extern const struct nv50_disp_chan_mthd g94_disp_core_chan_mthd;
extern const struct nv50_disp_chan_mthd g94_disp_core_mthd;
extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_base;
extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_dac;
......@@ -147,6 +165,6 @@ extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_sor;
extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_pior;
extern const struct nv50_disp_chan_mthd gf119_disp_base_mthd;
extern const struct nv50_disp_chan_mthd gk104_disp_core_chan_mthd;
extern const struct nv50_disp_chan_mthd gk104_disp_core_mthd;
extern const struct nv50_disp_chan_mthd gk104_disp_ovly_mthd;
#endif
drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c
View file @ 9b096283
......@@ -22,9 +22,6 @@
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_mthd_list
g84_disp_core_mthd_dac = {
......@@ -91,7 +88,7 @@ g84_disp_core_mthd_head = {
};
const struct nv50_disp_chan_mthd
g84_disp_core_chan_mthd = {
g84_disp_core_mthd = {
.name = "Core",
.addr = 0x000000,
.prev = 0x000004,
......@@ -105,13 +102,10 @@ g84_disp_core_chan_mthd = {
}
};
const struct nv50_disp_dmac_oclass
g84_disp_core_oclass = {
.base.oclass = G82_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &nv50_disp_core_func,
.mthd = &g84_disp_core_chan_mthd,
.chid = 0,
};
int
g84_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&nv50_disp_core_func, &g84_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c
View file @ 9b096283
......@@ -22,9 +22,6 @@
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
g94_disp_core_mthd_sor = {
......@@ -37,7 +34,7 @@ g94_disp_core_mthd_sor = {
};
const struct nv50_disp_chan_mthd
g94_disp_core_chan_mthd = {
g94_disp_core_mthd = {
.name = "Core",
.addr = 0x000000,
.prev = 0x000004,
......@@ -51,13 +48,10 @@ g94_disp_core_chan_mthd = {
}
};
const struct nv50_disp_dmac_oclass
g94_disp_core_oclass = {
.base.oclass = GT206_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &nv50_disp_core_func,
.mthd = &g94_disp_core_chan_mthd,
.chid = 0,
};
int
g94_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&nv50_disp_core_func, &g94_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c
View file @ 9b096283
......@@ -22,14 +22,9 @@
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
const struct nv50_disp_mthd_list
gf119_disp_core_mthd_base = {
.mthd = 0x0000,
......@@ -157,7 +152,7 @@ gf119_disp_core_mthd_head = {
};
static const struct nv50_disp_chan_mthd
gf119_disp_core_chan_mthd = {
gf119_disp_core_mthd = {
.name = "Core",
.addr = 0x000000,
.prev = -0x020000,
......@@ -232,13 +227,10 @@ gf119_disp_core_func = {
.bind = gf119_disp_dmac_bind,
};
const struct nv50_disp_dmac_oclass
gf119_disp_core_oclass = {
.base.oclass = GF110_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gf119_disp_core_chan_mthd,
.chid = 0,
};
int
gf119_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&gf119_disp_core_func, &gf119_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c
View file @ 9b096283
......@@ -22,9 +22,6 @@
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
gk104_disp_core_mthd_head = {
......@@ -106,7 +103,7 @@ gk104_disp_core_mthd_head = {
};
const struct nv50_disp_chan_mthd
gk104_disp_core_chan_mthd = {
gk104_disp_core_mthd = {
.name = "Core",
.addr = 0x000000,
.prev = -0x020000,
......@@ -120,13 +117,10 @@ gk104_disp_core_chan_mthd = {
}
};
const struct nv50_disp_dmac_oclass
gk104_disp_core_oclass = {
.base.oclass = GK104_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.chid = 0,
};
int
gk104_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&gf119_disp_core_func, &gk104_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk110.c deleted 100644 → 0
View file @ 6d41a753
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gk110_disp_core_oclass = {
.base.oclass = GK110_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.chid = 0,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregm107.c deleted 100644 → 0
View file @ 6d41a753
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gm107_disp_core_oclass = {
.base.oclass = GM107_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.chid = 0,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregm200.c deleted 100644 → 0
View file @ 6d41a753
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gm200_disp_core_oclass = {
.base.oclass = GM200_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.chid = 0,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp100.c deleted 100644 → 0
View file @ 6d41a753
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gp100_disp_core_oclass = {
.base.oclass = GP100_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.chid = 0,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c
View file @ 9b096283
......@@ -22,12 +22,9 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <subdev/timer.h>
#include <nvif/class.h>
static int
gp102_disp_core_init(struct nv50_disp_dmac *chan)
{
......@@ -66,13 +63,10 @@ gp102_disp_core_func = {
.bind = gf119_disp_dmac_bind,
};
const struct nv50_disp_dmac_oclass
gp102_disp_core_oclass = {
.base.oclass = GP102_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gp102_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.chid = 0,
};
int
gp102_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&gp102_disp_core_func, &gk104_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregt200.c deleted 100644 → 0
View file @ 6d41a753
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gt200_disp_core_oclass = {
.base.oclass = GT200_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &nv50_disp_core_func,
.mthd = &g84_disp_core_chan_mthd,
.chid = 0,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/coregt215.c deleted 100644 → 0
View file @ 6d41a753
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gt215_disp_core_oclass = {
.base.oclass = GT214_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &nv50_disp_core_func,
.mthd = &g94_disp_core_chan_mthd,
.chid = 0,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c
View file @ 9b096283
......@@ -22,31 +22,29 @@
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/cl507d.h>
#include <nvif/unpack.h>
int
nv50_disp_core_new(const struct nv50_disp_dmac_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp_root *root, int chid,
const struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv50_disp_core_new_(const struct nv50_disp_dmac_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp *disp, int chid,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
union {
struct nv50_disp_core_channel_dma_v0 v0;
} *args = data;
} *args = argv;
struct nvkm_object *parent = oclass->parent;
u64 push;
int ret = -ENOSYS;
nvif_ioctl(parent, "create disp core channel dma size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create disp core channel dma size %d\n", argc);
if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create disp core channel dma vers %d "
"pushbuf %016llx\n",
args->v0.version, args->v0.pushbuf);
......@@ -54,7 +52,7 @@ nv50_disp_core_new(const struct nv50_disp_dmac_func *func,
} else
return ret;
return nv50_disp_dmac_new_(func, mthd, root->disp, chid, 0,
return nv50_disp_dmac_new_(func, mthd, disp, chid, 0,
push, oclass, pobject);
}
......@@ -151,7 +149,7 @@ nv50_disp_core_mthd_head = {
};
static const struct nv50_disp_chan_mthd
nv50_disp_core_chan_mthd = {
nv50_disp_core_mthd = {
.name = "Core",
.addr = 0x000000,
.prev = 0x000004,
......@@ -231,13 +229,10 @@ nv50_disp_core_func = {
.bind = nv50_disp_dmac_bind,
};
const struct nv50_disp_dmac_oclass
nv50_disp_core_oclass = {
.base.oclass = NV50_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &nv50_disp_core_func,
.mthd = &nv50_disp_core_chan_mthd,
.chid = 0,
};
int
nv50_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_core_new_(&nv50_disp_core_func, &nv50_disp_core_mthd,
disp, 0, oclass, argv, argc, pobject);
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.h
View file @ 9b096283
......@@ -32,46 +32,4 @@ extern const struct nv50_disp_dmac_func gf119_disp_core_func;
void gf119_disp_core_fini(struct nv50_disp_dmac *);
extern const struct nv50_disp_dmac_func gp102_disp_dmac_func;
struct nv50_disp_dmac_oclass {
int (*ctor)(const struct nv50_disp_dmac_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp_root *, int chid,
const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
struct nvkm_sclass base;
const struct nv50_disp_dmac_func *func;
const struct nv50_disp_chan_mthd *mthd;
int chid;
};
int nv50_disp_core_new(const struct nv50_disp_dmac_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp_root *, int chid,
const struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **);
extern const struct nv50_disp_dmac_oclass nv50_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass g84_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass g94_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gt200_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gt215_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gf119_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gk104_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gk110_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gm107_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gm200_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gp100_disp_core_oclass;
extern const struct nv50_disp_dmac_oclass gp102_disp_core_oclass;
#endif
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
View file @ 9b096283
......@@ -24,6 +24,7 @@
#include "nv50.h"
#include "head.h"
#include "ior.h"
#include "channv50.h"
#include "rootnv50.h"
#include <core/client.h>
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
g84_disp_root = {
.dmac = {
&g84_disp_core_oclass,
},
.user = {
{{0,0,G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,G82_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,G82_DISP_CORE_CHANNEL_DMA }, g84_disp_core_new },
{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
g94_disp_root = {
.dmac = {
&g94_disp_core_oclass,
},
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT206_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gf119_disp_root = {
.dmac = {
&gf119_disp_core_oclass,
},
.user = {
{{0,0,GF110_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GF110_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GF110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GF110_DISP_CORE_CHANNEL_DMA }, gf119_disp_core_new },
{{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gk104_disp_root = {
.dmac = {
&gk104_disp_core_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK104_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gk110_disp_root = {
.dmac = {
&gk110_disp_core_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK110_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gm107_disp_root = {
.dmac = {
&gm107_disp_core_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GM107_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gm200_disp_root = {
.dmac = {
&gm200_disp_core_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GM200_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gp100_disp_root = {
.dmac = {
&gp100_disp_core_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GP100_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gp102_disp_root = {
.dmac = {
&gp102_disp_core_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gp102_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gp102_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gp102_disp_base_new },
{{0,0,GP102_DISP_CORE_CHANNEL_DMA }, gp102_disp_core_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gt200_disp_root = {
.dmac = {
&gt200_disp_core_oclass,
},
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT200_DISP_CORE_CHANNEL_DMA }, g84_disp_core_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c
View file @ 9b096283
......@@ -28,13 +28,11 @@
static const struct nv50_disp_root_func
gt215_disp_root = {
.dmac = {
&gt215_disp_core_oclass,
},
.user = {
{{0,0,GT214_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,GT214_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT214_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT214_DISP_CORE_CHANNEL_DMA }, g94_disp_core_new },
{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
View file @ 9b096283
......@@ -268,16 +268,6 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
return -EINVAL;
}
static int
nv50_disp_root_dmac_new_(const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
const struct nv50_disp_dmac_oclass *sclass = oclass->priv;
struct nv50_disp_root *root = nv50_disp_root(oclass->parent);
return sclass->ctor(sclass->func, sclass->mthd, root, sclass->chid,
oclass, data, size, pobject);
}
static int
nv50_disp_root_child_new_(const struct nvkm_oclass *oclass,
void *argv, u32 argc, struct nvkm_object **pobject)
......@@ -293,15 +283,6 @@ nv50_disp_root_child_get_(struct nvkm_object *object, int index,
{
struct nv50_disp_root *root = nv50_disp_root(object);
if (index < ARRAY_SIZE(root->func->dmac)) {
sclass->base = root->func->dmac[index]->base;
sclass->priv = root->func->dmac[index];
sclass->ctor = nv50_disp_root_dmac_new_;
return 0;
}
index -= ARRAY_SIZE(root->func->dmac);
if (root->func->user[index].ctor) {
sclass->base = root->func->user[index].base;
sclass->priv = root->func->user + index;
......@@ -347,13 +328,11 @@ nv50_disp_root_new_(const struct nv50_disp_root_func *func,
static const struct nv50_disp_root_func
nv50_disp_root = {
.dmac = {
&nv50_disp_core_oclass,
},
.user = {
{{0,0,NV50_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,NV50_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,NV50_DISP_BASE_CHANNEL_DMA }, nv50_disp_base_new },
{{0,0,NV50_DISP_CORE_CHANNEL_DMA }, nv50_disp_core_new },
{{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new },
{}
},
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
View file @ 9b096283
......@@ -12,7 +12,7 @@ struct nv50_disp_root {
};
struct nv50_disp_root_func {
const struct nv50_disp_dmac_oclass *dmac[1];
int blah;
struct nv50_disp_user {
struct nvkm_sclass base;
int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc,
......
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