Commit 9bbad6fd authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher

drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a51dca4f
...@@ -55,6 +55,25 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) ...@@ -55,6 +55,25 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
upper_32_bits(value)); upper_32_bits(value));
} }
static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
{
gfxhub_v1_0_init_gart_pt_regs(adev);
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
(u32)(adev->mc.gtt_start >> 12));
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
(u32)(adev->mc.gtt_start >> 44));
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
(u32)(adev->mc.gtt_end >> 12));
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
(u32)(adev->mc.gtt_end >> 44));
}
int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
{ {
u32 tmp; u32 tmp;
...@@ -62,9 +81,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) ...@@ -62,9 +81,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
u32 i; u32 i;
/* Program MC. */ /* Program MC. */
gfxhub_v1_0_init_gart_pt_regs(adev); gfxhub_v1_0_init_gart_aperture_regs(adev);
/* Update configuration */
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR), WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
adev->mc.vram_start >> 18); adev->mc.vram_start >> 18);
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR), WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
...@@ -165,21 +183,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) ...@@ -165,21 +183,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
0); 0);
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp); WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
/* setup context0 */
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
(u32)(adev->mc.gtt_start >> 12));
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
(u32)(adev->mc.gtt_start >> 44));
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
(u32)(adev->mc.gtt_end >> 12));
WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
(u32)(adev->mc.gtt_end >> 44));
WREG32(SOC15_REG_OFFSET(GC, 0, WREG32(SOC15_REG_OFFSET(GC, 0,
mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32), mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
(u32)(adev->dummy_page.addr >> 12)); (u32)(adev->dummy_page.addr >> 12));
......
...@@ -66,6 +66,25 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) ...@@ -66,6 +66,25 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
upper_32_bits(value)); upper_32_bits(value));
} }
static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
{
mmhub_v1_0_init_gart_pt_regs(adev);
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
(u32)(adev->mc.gtt_start >> 12));
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
(u32)(adev->mc.gtt_start >> 44));
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
(u32)(adev->mc.gtt_end >> 12));
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
(u32)(adev->mc.gtt_end >> 44));
}
int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
{ {
u32 tmp; u32 tmp;
...@@ -75,6 +94,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) ...@@ -75,6 +94,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
/* Program MC. */ /* Program MC. */
mmhub_v1_0_init_gart_pt_regs(adev); mmhub_v1_0_init_gart_pt_regs(adev);
mmhub_v1_0_init_gart_aperture_regs(adev);
/* Update configuration */ /* Update configuration */
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR), WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
...@@ -176,21 +196,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) ...@@ -176,21 +196,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
0); 0);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp); WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
/* setup context0 */
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
(u32)(adev->mc.gtt_start >> 12));
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
(u32)(adev->mc.gtt_start >> 44));
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
(u32)(adev->mc.gtt_end >> 12));
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
(u32)(adev->mc.gtt_end >> 44));
WREG32(SOC15_REG_OFFSET(MMHUB, 0, WREG32(SOC15_REG_OFFSET(MMHUB, 0,
mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32), mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
(u32)(adev->dummy_page.addr >> 12)); (u32)(adev->dummy_page.addr >> 12));
......
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