Commit 9be1c8af authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard

clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver

Allwinner H5 is a SoC that features a design which keeps the peripheral
compatible with H3, so that it have also a CCU like the one on H3 --
only one bus gate/reset is added, and the mmc sample/output phases are
removed because of MMC controller update.

Add its support in our existing H3 CCU driver.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 845d6b0f
...@@ -10,6 +10,7 @@ Required properties : ...@@ -10,6 +10,7 @@ Required properties :
- "allwinner,sun8i-v3s-ccu" - "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu" - "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu" - "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-h5-ccu"
- reg: Must contain the registers base address and length - reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed: - clocks: phandle to the oscillators feeding the CCU. Two are needed:
......
...@@ -119,7 +119,7 @@ config SUN8I_H3_CCU ...@@ -119,7 +119,7 @@ config SUN8I_H3_CCU
select SUNXI_CCU_NM select SUNXI_CCU_NM
select SUNXI_CCU_MP select SUNXI_CCU_MP
select SUNXI_CCU_PHASE select SUNXI_CCU_PHASE
default MACH_SUN8I default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
config SUN8I_V3S_CCU config SUN8I_V3S_CCU
bool "Support for the Allwinner V3s CCU" bool "Support for the Allwinner V3s CCU"
......
This diff is collapsed.
...@@ -57,6 +57,7 @@ ...@@ -57,6 +57,7 @@
/* And the GPU module clock is exported */ /* And the GPU module clock is exported */
#define CLK_NUMBER (CLK_GPU + 1) #define CLK_NUMBER_H3 (CLK_GPU + 1)
#define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1)
#endif /* _CCU_SUN8I_H3_H_ */ #endif /* _CCU_SUN8I_H3_H_ */
...@@ -91,7 +91,7 @@ ...@@ -91,7 +91,7 @@
#define CLK_BUS_UART1 63 #define CLK_BUS_UART1 63
#define CLK_BUS_UART2 64 #define CLK_BUS_UART2 64
#define CLK_BUS_UART3 65 #define CLK_BUS_UART3 65
#define CLK_BUS_SCR 66 #define CLK_BUS_SCR0 66
#define CLK_BUS_EPHY 67 #define CLK_BUS_EPHY 67
#define CLK_BUS_DBG 68 #define CLK_BUS_DBG 68
...@@ -142,4 +142,7 @@ ...@@ -142,4 +142,7 @@
#define CLK_GPU 114 #define CLK_GPU 114
/* New clocks imported in H5 */
#define CLK_BUS_SCR1 115
#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ #endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
...@@ -98,6 +98,9 @@ ...@@ -98,6 +98,9 @@
#define RST_BUS_UART1 50 #define RST_BUS_UART1 50
#define RST_BUS_UART2 51 #define RST_BUS_UART2 51
#define RST_BUS_UART3 52 #define RST_BUS_UART3 52
#define RST_BUS_SCR 53 #define RST_BUS_SCR0 53
/* New resets imported in H5 */
#define RST_BUS_SCR1 54
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ #endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
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