Commit 9c0fed84 authored by Dave Airlie's avatar Dave Airlie

Merge tag 'drm-intel-next-2021-04-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Features:
- Add support for FBs requiring a power-of-two stride padding (Imre)

Refactoring:
- Disassociate display version from gen (Matt)
- Refactor legacy DP and HDMI code to separate files (Ville)
- Refactor FB plane code to a separate file (Imre)
- Refactor VBT child device info parsing and usage (Jani)
- Refactor KBL/TGL/ADL-S display and gt stepping schemes (Jani)

Fixes:
- DP Link-Training Tunable PHY Repeaters (LTTPR) fixes (Imre)
- HDCP fixes (Anshuman)
- DP 2.0 HDMI 2.1 PCON Fixed Rate Link (FRL) fixes (Ankit)
- Set HDA link parameters in driver (Kai)
- Fix enabled_planes bitmask (Ville)
- Fix transposed arguments to skl_plane_wm_level() (Ville)
- Stop adding planes to the commit needlessly (Ville)
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87v996ml17.fsf@intel.com
parents 41d1d0c5 81f1f8f1
......@@ -2635,14 +2635,16 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
* @aux: DisplayPort AUX channel
* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
* @concurrent_mode: true if concurrent mode or operation is required,
* false otherwise.
* @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
* In Concurrent Mode, the FRL link bring up can be done along with
* DP Link training. In Sequential mode, the FRL link bring up is done prior to
* the DP Link training.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
bool concurrent_mode)
u8 frl_mode)
{
int ret;
u8 buf;
......@@ -2651,7 +2653,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
if (ret < 0)
return ret;
if (concurrent_mode)
if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
else
buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
......@@ -2694,21 +2696,23 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
* @aux: DisplayPort AUX channel
* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
* @extended_train_mode : true for Extended Mode, false for Normal Mode.
* In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
* from min, and stops when link training is successful. In Extended mode, all
* frl bw selected in the mask are trained by the PCON.
* @frl_type : FRL training type, can be Extended, or Normal.
* In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
* starting from min, and stops when link training is successful. In Extended
* FRL training, all frl bw selected in the mask are trained by the PCON.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
bool extended_train_mode)
u8 frl_type)
{
int ret;
u8 buf = max_frl_mask;
if (extended_train_mode)
if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
else
buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
if (ret < 0)
......
......@@ -52,6 +52,7 @@ i915-y += i915_drv.o \
intel_pm.o \
intel_runtime_pm.o \
intel_sideband.o \
intel_step.o \
intel_uncore.o \
intel_wakeref.o \
vlv_suspend.o
......@@ -208,6 +209,7 @@ i915-y += \
display/intel_dpll.o \
display/intel_dpll_mgr.o \
display/intel_dsb.o \
display/intel_fb.o \
display/intel_fbc.o \
display/intel_fdi.o \
display/intel_fifo_underrun.o \
......@@ -239,6 +241,8 @@ i915-y += \
display/dvo_ns2501.o \
display/dvo_sil164.o \
display/dvo_tfp410.o \
display/g4x_dp.o \
display/g4x_hdmi.o \
display/icl_dsi.o \
display/intel_crt.o \
display/intel_ddi.o \
......
This diff is collapsed.
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2020 Intel Corporation
*/
#ifndef _G4X_DP_H_
#define _G4X_DP_H_
#include <linux/types.h>
#include "i915_reg.h"
enum pipe;
enum port;
struct drm_i915_private;
struct intel_crtc_state;
struct intel_dp;
struct intel_encoder;
const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
enum pipe vlv_active_pipe(struct intel_dp *intel_dp);
void g4x_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
i915_reg_t dp_reg, enum port port,
enum pipe *pipe);
bool g4x_dp_init(struct drm_i915_private *dev_priv,
i915_reg_t output_reg, enum port port);
#endif
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/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2020 Intel Corporation
*/
#ifndef _G4X_HDMI_H_
#define _G4X_HDMI_H_
#include <linux/types.h>
#include "i915_reg.h"
enum port;
struct drm_i915_private;
void g4x_hdmi_init(struct drm_i915_private *dev_priv,
i915_reg_t hdmi_reg, enum port port);
#endif
This diff is collapsed.
......@@ -457,7 +457,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
tmp = intel_de_read(dev_priv,
ICL_PORT_PCS_DW1_AUX(phy));
tmp &= ~LATENCY_OPTIM_MASK;
......@@ -592,7 +592,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
* a value '0' inside TA_PARAM_REGISTERS otherwise
* leave all fields at HW default values.
*/
if (IS_GEN(dev_priv, 11)) {
if (IS_DISPLAY_VER(dev_priv, 11)) {
if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
tmp = intel_de_read(dev_priv,
......@@ -692,7 +692,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
for_each_dsi_phy(phy, intel_dsi->phys) {
if (INTEL_GEN(dev_priv) >= 12)
if (DISPLAY_VER(dev_priv) >= 12)
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
else
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
......@@ -774,7 +774,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
}
}
if (INTEL_GEN(dev_priv) >= 12) {
if (DISPLAY_VER(dev_priv) >= 12) {
if (is_vid_mode(intel_dsi))
tmp |= BLANKING_PACKET_ENABLE;
}
......@@ -1020,7 +1020,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
}
/* program TRANS_VBLANK register, should be same as vtotal programmed */
if (INTEL_GEN(dev_priv) >= 12) {
if (DISPLAY_VER(dev_priv) >= 12) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
intel_de_write(dev_priv, VBLANK(dsi_trans),
......@@ -1158,7 +1158,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
gen11_dsi_configure_transcoder(encoder, crtc_state);
/* Step 4l: Gate DDI clocks */
if (IS_GEN(dev_priv, 11))
if (IS_DISPLAY_VER(dev_priv, 11))
gen11_dsi_gate_clocks(encoder);
}
......@@ -1534,7 +1534,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
bool use_dsc;
int ret;
......
......@@ -332,8 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
plane_state->hw.fb->format->is_yuv &&
plane_state->hw.fb->format->num_planes > 1) {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
if (IS_DISPLAY_VER(dev_priv, 9)) {
mode = SKL_PS_SCALER_MODE_NV12;
} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
/*
......@@ -351,7 +350,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
if (linked)
mode |= PS_PLANE_Y_SEL(linked->id);
}
} else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
} else if (DISPLAY_VER(dev_priv) >= 10) {
mode = PS_SCALER_MODE_NORMAL;
} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
/*
......@@ -460,7 +459,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
* isn't necessary to change between HQ and dyn mode
* on those platforms.
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
if (DISPLAY_VER(dev_priv) >= 10)
continue;
plane = drm_plane_from_index(&dev_priv->drm, i);
......
......@@ -317,12 +317,13 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
new_crtc_state->enabled_planes |= BIT(plane->id);
ret = plane->check_plane(new_crtc_state, new_plane_state);
if (ret)
return ret;
if (fb)
new_crtc_state->enabled_planes |= BIT(plane->id);
/* FIXME pre-g4x don't work like this */
if (new_plane_state->uapi.visible)
new_crtc_state->active_planes |= BIT(plane->id);
......
......@@ -248,7 +248,7 @@ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_sta
break;
}
if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
i = ARRAY_SIZE(hdmi_audio_clock);
if (i == ARRAY_SIZE(hdmi_audio_clock)) {
......@@ -586,14 +586,14 @@ static void enable_audio_dsc_wa(struct intel_encoder *encoder,
unsigned int hblank_early_prog, samples_room;
unsigned int val;
if (INTEL_GEN(i915) < 11)
if (DISPLAY_VER(i915) < 11)
return;
val = intel_de_read(i915, AUD_CONFIG_BE);
if (INTEL_GEN(i915) == 11)
if (IS_DISPLAY_VER(i915, 11))
val |= HBLANK_EARLY_ENABLE_ICL(pipe);
else if (INTEL_GEN(i915) >= 12)
else if (DISPLAY_VER(i915) >= 12)
val |= HBLANK_EARLY_ENABLE_TGL(pipe);
if (crtc_state->dsc.compression_enable &&
......@@ -933,7 +933,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
......@@ -1010,7 +1010,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
if (dev_priv->audio_power_refcount++ == 0) {
if (INTEL_GEN(dev_priv) >= 9) {
if (DISPLAY_VER(dev_priv) >= 9) {
intel_de_write(dev_priv, AUD_FREQ_CNTRL,
dev_priv->audio_freq_cntrl);
drm_dbg_kms(&dev_priv->drm,
......@@ -1022,7 +1022,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, true);
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
if (DISPLAY_VER(dev_priv) >= 10)
intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
(intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
}
......@@ -1050,7 +1050,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
unsigned long cookie;
u32 tmp;
if (INTEL_GEN(dev_priv) < 9)
if (DISPLAY_VER(dev_priv) < 9)
return;
cookie = i915_audio_component_get_power(kdev);
......@@ -1266,6 +1266,15 @@ static const struct component_ops i915_audio_component_bind_ops = {
.unbind = i915_audio_component_unbind,
};
#define AUD_FREQ_TMODE_SHIFT 14
#define AUD_FREQ_4T 0
#define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT)
#define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11)
#define AUD_FREQ_BCLK_96M BIT(4)
#define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M)
#define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M)
/**
* i915_audio_component_init - initialize and register the audio component
* @dev_priv: i915 device instance
......@@ -1284,6 +1293,7 @@ static const struct component_ops i915_audio_component_bind_ops = {
*/
static void i915_audio_component_init(struct drm_i915_private *dev_priv)
{
u32 aud_freq, aud_freq_init;
int ret;
ret = component_add_typed(dev_priv->drm.dev,
......@@ -1296,12 +1306,22 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
return;
}
if (INTEL_GEN(dev_priv) >= 9) {
dev_priv->audio_freq_cntrl = intel_de_read(dev_priv,
AUD_FREQ_CNTRL);
drm_dbg_kms(&dev_priv->drm,
"init value of AUD_FREQ_CNTRL of 0x%x\n",
dev_priv->audio_freq_cntrl);
if (DISPLAY_VER(dev_priv) >= 9) {
aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL);
if (INTEL_GEN(dev_priv) >= 12)
aud_freq = AUD_FREQ_GEN12;
else
aud_freq = aud_freq_init;
/* use BIOS provided value for TGL unless it is a known bad value */
if (IS_TIGERLAKE(dev_priv) && aud_freq_init != AUD_FREQ_TGL_BROKEN)
aud_freq = aud_freq_init;
drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
aud_freq, aud_freq_init);
dev_priv->audio_freq_cntrl = aud_freq;
}
dev_priv->audio_component_registered = true;
......
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......@@ -33,6 +33,7 @@
#include <linux/types.h>
struct drm_i915_private;
struct intel_bios_encoder_data;
struct intel_crtc_state;
struct intel_encoder;
enum port;
......@@ -249,14 +250,20 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
int dsc_max_bpc);
int intel_bios_max_tmds_clock(struct intel_encoder *encoder);
int intel_bios_hdmi_level_shift(struct intel_encoder *encoder);
int intel_bios_dp_boost_level(struct intel_encoder *encoder);
int intel_bios_hdmi_boost_level(struct intel_encoder *encoder);
int intel_bios_dp_max_link_rate(struct intel_encoder *encoder);
int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder);
bool intel_bios_port_supports_dvi(struct drm_i915_private *i915, enum port port);
bool intel_bios_port_supports_hdmi(struct drm_i915_private *i915, enum port port);
bool intel_bios_port_supports_dp(struct drm_i915_private *i915, enum port port);
bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port);
bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port);
const struct intel_bios_encoder_data *
intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port);
bool intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata);
bool intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata);
bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata);
bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata);
int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata);
#endif /* _INTEL_BIOS_H_ */
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......@@ -11,7 +11,6 @@
enum pipe;
struct drm_encoder;
struct drm_i915_private;
struct drm_i915_private;
bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
i915_reg_t adpa_reg, enum pipe *pipe);
......
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