Commit 9cbe40c1 authored by Vijay Purushothaman's avatar Vijay Purushothaman Committed by Daniel Vetter

drm/i915: Update prop, int co-eff and gain threshold for CHV

This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.

v2: Split the original changes into multiple smaller patches based on
review by Ville

v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.

v4: TDC target cnt is 10 bits and not 8 bits (Ville)
Signed-off-by: default avatarVijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent de3a0fde
...@@ -1041,6 +1041,8 @@ enum skl_disp_power_wells { ...@@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW8_CH0 0x8020 #define _CHV_PLL_DW8_CH0 0x8020
#define _CHV_PLL_DW8_CH1 0x81A0 #define _CHV_PLL_DW8_CH1 0x81A0
#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
#define _CHV_PLL_DW9_CH0 0x8024 #define _CHV_PLL_DW9_CH0 0x8024
......
...@@ -6159,10 +6159,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc, ...@@ -6159,10 +6159,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc->pipe; int pipe = crtc->pipe;
int dpll_reg = DPLL(crtc->pipe); int dpll_reg = DPLL(crtc->pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe); enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff; u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val; u32 dpio_val;
int refclk; int vco;
bestn = pipe_config->dpll.n; bestn = pipe_config->dpll.n;
bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
...@@ -6170,7 +6170,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc, ...@@ -6170,7 +6170,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22; bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1; bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2; bestp2 = pipe_config->dpll.p2;
vco = pipe_config->dpll.vco;
dpio_val = 0; dpio_val = 0;
loopfilter = 0;
/* /*
* Enable Refclk and SSC * Enable Refclk and SSC
...@@ -6217,18 +6219,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc, ...@@ -6217,18 +6219,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
/* Loop filter */ /* Loop filter */
refclk = i9xx_get_refclk(crtc, 0); if (vco == 5400000) {
loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
2 << DPIO_CHV_GAIN_CTRL_SHIFT; loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
if (refclk == 100000) loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
intcoeff = 11; tribuf_calcntr = 0x9;
else if (refclk == 38400) } else if (vco <= 6200000) {
intcoeff = 10; loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
else loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
intcoeff = 9; loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; tribuf_calcntr = 0x9;
} else if (vco <= 6480000) {
loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
tribuf_calcntr = 0x8;
} else {
/* Not supported. Apply the same limits as in the max case */
loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
tribuf_calcntr = 0;
}
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
/* AFC Recal */ /* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment