[ARM PATCH] 2404/1: BTAC/BTB flushing added in cpu_v6_switch_mm

Patch from Catalin Marinas

This is needed since ARMv6 branch prediction tagging is done by the
virtual address and the ASIDs aren't taken into account.

Signed-off-by: Catalin Marinas
Signed-off-by: Russell King

arch/arm/mm/proc-v6.S

@@ -105,6 +105,7 @@ ENTRY(cpu_v6_dcache_clean_area)
 ENTRY(cpu_v6_switch_mm)
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
+	mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
 	mcr	p15, 0, r1, c13, c0, 1		@ set context ID