staging: brcm80211: various __iomem additions to softmac.

So it is clear to the reader what memory is IO mapped
Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Franky Lin <frankyl@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

drivers/staging/brcm80211/brcmsmac/aiutils.h

@@ -269,8 +269,8 @@ struct si_info {
 	char *vars;
 	uint varsz;
 
-	void *curmap;		/* current regs va */
-	void *regs[SI_MAXCORES];	/* other regs va */
+	void __iomem *curmap;			/* current regs va */
+	void __iomem *regs[SI_MAXCORES];	/* other regs va */
 
 	uint curidx;		/* current core index */
 	uint numcores;		/* # discovered cores */
@@ -319,8 +319,8 @@ extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
 extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
 
 /* === exported functions === */
-extern struct si_pub *ai_attach(void *regs, struct pci_dev *sdh, char **vars,
-				uint *varsz);
+extern struct si_pub *ai_attach(void __iomem *regs, struct pci_dev *sdh,
+				char **vars, uint *varsz);
 extern void ai_detach(struct si_pub *sih);
 extern uint ai_coreid(struct si_pub *sih);
 extern uint ai_corerev(struct si_pub *sih);
@@ -331,10 +331,10 @@ extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
 extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
 extern bool ai_iscoreup(struct si_pub *sih);
 extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
-extern void *ai_setcoreidx(struct si_pub *sih, uint coreidx);
-extern void *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
-extern void *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
-			    uint *intr_val);
+extern void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx);
+extern void __iomem *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
+extern void __iomem *ai_switch_core(struct si_pub *sih, uint coreid,
+				    uint *origidx, uint *intr_val);
 extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
 extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
 extern void ai_core_disable(struct si_pub *sih, u32 bits);

drivers/staging/brcm80211/brcmsmac/main.c

@@ -4678,7 +4678,7 @@ struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
  *    put the whole chip in reset(driver down state), no clock
  */
 static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
-			  uint unit, bool piomode, void *regsva,
+			  uint unit, bool piomode, void __iomem *regsva,
 			  struct pci_dev *btparam)
 {
 	struct brcms_hardware *wlc_hw;

drivers/staging/brcm80211/brcmsmac/nicpci.c

@@ -206,8 +206,8 @@ struct sbpcieregs {
 
 struct pcicore_info {
 	union {
-		struct sbpcieregs *pcieregs;
-		struct sbpciregs *pciregs;
+		struct sbpcieregs __iomem *pcieregs;
+		struct sbpciregs __iomem *pciregs;
 	} regs;			/* Memory mapped register to the core */
 
 	struct si_pub *sih;	/* System interconnect handle */
@@ -239,7 +239,7 @@ static void pr28829_delay(void)
  * It's caller's responsibility to make sure that this is done only once
  */
 struct pcicore_info *pcicore_init(struct si_pub *sih, struct pci_dev *pdev,
-				  void *regs)
+				  void __iomem *regs)
 {
 	struct pcicore_info *pi;
 
@@ -334,7 +334,7 @@ pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
 
 /* ***** Register Access API */
 static uint
-pcie_readreg(struct sbpcieregs *pcieregs, uint addrtype, uint offset)
+pcie_readreg(struct sbpcieregs __iomem *pcieregs, uint addrtype, uint offset)
 {
 	uint retval = 0xFFFFFFFF;
 
@@ -354,8 +354,8 @@ pcie_readreg(struct sbpcieregs *pcieregs, uint addrtype, uint offset)
 	return retval;
 }
 
-static uint
-pcie_writereg(struct sbpcieregs *pcieregs, uint addrtype, uint offset, uint val)
+static uint pcie_writereg(struct sbpcieregs __iomem *pcieregs, uint addrtype,
+			  uint offset, uint val)
 {
 	switch (addrtype) {
 	case PCIE_CONFIGREGS:
@@ -374,7 +374,7 @@ pcie_writereg(struct sbpcieregs *pcieregs, uint addrtype, uint offset, uint val)
 
 static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
 {
-	struct sbpcieregs *pcieregs = pi->regs.pcieregs;
+	struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
 	uint mdiodata, i = 0;
 	uint pcie_serdes_spinwait = 200;
 
@@ -405,7 +405,7 @@ static int
 pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
 	    uint *val)
 {
-	struct sbpcieregs *pcieregs = pi->regs.pcieregs;
+	struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
 	uint mdiodata;
 	uint i = 0;
 	uint pcie_serdes_spinwait = 10;
@@ -503,7 +503,7 @@ static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
 {
 	u32 w;
 	struct si_pub *sih = pi->sih;
-	struct sbpcieregs *pcieregs = pi->regs.pcieregs;
+	struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
 
 	if (sih->buscoretype != PCIE_CORE_ID || sih->buscorerev < 7)
 		return;
@@ -582,9 +582,10 @@ static void pcie_war_polarity(struct pcicore_info *pi)
  */
 static void pcie_war_aspm_clkreq(struct pcicore_info *pi)
 {
-	struct sbpcieregs *pcieregs = pi->regs.pcieregs;
+	struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
 	struct si_pub *sih = pi->sih;
-	u16 val16, *reg16;
+	u16 val16;
+	u16 __iomem *reg16;
 	u32 w;
 
 	if (!PCIE_ASPM(sih))
@@ -642,8 +643,9 @@ static void pcie_war_serdes(struct pcicore_info *pi)
 /* Needs to happen when coming out of 'standby'/'hibernate' */
 static void pcie_misc_config_fixup(struct pcicore_info *pi)
 {
-	struct sbpcieregs *pcieregs = pi->regs.pcieregs;
-	u16 val16, *reg16;
+	struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
+	u16 val16;
+	u16 __iomem *reg16;
 
 	reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
 	val16 = R_REG(reg16);
@@ -658,8 +660,8 @@ static void pcie_misc_config_fixup(struct pcicore_info *pi)
 /* Needs to happen when coming out of 'standby'/'hibernate' */
 static void pcie_war_noplldown(struct pcicore_info *pi)
 {
-	struct sbpcieregs *pcieregs = pi->regs.pcieregs;
-	u16 *reg16;
+	struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
+	u16 __iomem *reg16;
 
 	/* turn off serdes PLL down */
 	ai_corereg(pi->sih, SI_CC_IDX, offsetof(struct chipcregs, chipcontrol),
@@ -674,7 +676,7 @@ static void pcie_war_noplldown(struct pcicore_info *pi)
 static void pcie_war_pci_setup(struct pcicore_info *pi)
 {
 	struct si_pub *sih = pi->sih;
-	struct sbpcieregs *pcieregs = pi->regs.pcieregs;
+	struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
 	u32 w;
 
 	if (sih->buscorerev == 0 || sih->buscorerev == 1) {
@@ -789,7 +791,7 @@ void pcicore_down(struct pcicore_info *pi, int state)
 }
 
 /* precondition: current core is sii->buscoretype */
-static void pcicore_fixcfg(struct pcicore_info *pi, u16 *reg16)
+static void pcicore_fixcfg(struct pcicore_info *pi, u16 __iomem *reg16)
 {
 	struct si_info *sii = (struct si_info *)(pi->sih);
 	u16 val16;
@@ -804,18 +806,21 @@ static void pcicore_fixcfg(struct pcicore_info *pi, u16 *reg16)
 	}
 }
 
-void pcicore_fixcfg_pci(struct pcicore_info *pi, struct sbpciregs *pciregs)
+void
+pcicore_fixcfg_pci(struct pcicore_info *pi, struct sbpciregs __iomem *pciregs)
 {
 	pcicore_fixcfg(pi, &pciregs->sprom[SRSH_PI_OFFSET]);
 }
 
-void pcicore_fixcfg_pcie(struct pcicore_info *pi, struct sbpcieregs *pcieregs)
+void pcicore_fixcfg_pcie(struct pcicore_info *pi,
+			 struct sbpcieregs __iomem *pcieregs)
 {
 	pcicore_fixcfg(pi, &pcieregs->sprom[SRSH_PI_OFFSET]);
 }
 
 /* precondition: current core is pci core */
-void pcicore_pci_setup(struct pcicore_info *pi, struct sbpciregs *pciregs)
+void
+pcicore_pci_setup(struct pcicore_info *pi, struct sbpciregs __iomem *pciregs)
 {
 	u32 w;
 

drivers/staging/brcm80211/brcmsmac/nicpci.h

@@ -62,7 +62,8 @@ struct sbpciregs;
 struct sbpcieregs;
 
 extern struct pcicore_info *pcicore_init(struct si_pub *sih,
-					 struct pci_dev *pdev, void *regs);
+					 struct pci_dev *pdev,
+					 void __iomem *regs);
 extern void pcicore_deinit(struct pcicore_info *pch);
 extern void pcicore_attach(struct pcicore_info *pch, char *pvars, int state);
 extern void pcicore_hwup(struct pcicore_info *pch);
@@ -72,10 +73,10 @@ extern void pcicore_down(struct pcicore_info *pch, int state);
 extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
 				      unsigned char *buf, u32 *buflen);
 extern void pcicore_fixcfg_pci(struct pcicore_info *pch,
-			       struct sbpciregs *pciregs);
+			       struct sbpciregs __iomem *pciregs);
 extern void pcicore_fixcfg_pcie(struct pcicore_info *pch,
-				struct sbpcieregs *pciregs);
+				struct sbpcieregs __iomem *pciregs);
 extern void pcicore_pci_setup(struct pcicore_info *pch,
-			      struct sbpciregs *pciregs);
+			      struct sbpciregs __iomem *pciregs);
 
 #endif /* _BRCM_NICPCI_H_ */

drivers/staging/brcm80211/brcmsmac/otp.c

@@ -132,7 +132,8 @@ struct otpinfo {
 #define OTP4315_SWREG_SZ	178	/* 178 bytes */
 #define OTP_SZ_FU_144		(144/8)	/* 144 bits */
 
-static u16 ipxotp_otpr(struct otpinfo *oi, struct chipcregs *cc, uint wn)
+static u16
+ipxotp_otpr(struct otpinfo *oi, struct chipcregs __iomem *cc, uint wn)
 {
 	return R_REG(&cc->sromotp[wn]);
 }
@@ -160,7 +161,7 @@ static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
 	return ret;
 }
 
-static void _ipxotp_init(struct otpinfo *oi, struct chipcregs *cc)
+static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc)
 {
 	uint k;
 	u32 otpp, st;
@@ -240,7 +241,7 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs *cc)
 static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
 {
 	uint idx;
-	struct chipcregs *cc;
+	struct chipcregs __iomem *cc;
 
 	/* Make sure we're running IPX OTP */
 	if (!OTPTYPE_IPX(sih->ccrev))
@@ -295,7 +296,7 @@ static int
 ipxotp_read_region(struct otpinfo *oi, int region, u16 *data, uint *wlen)
 {
 	uint idx;
-	struct chipcregs *cc;
+	struct chipcregs __iomem *cc;
 	uint base, i, sz;
 
 	/* Validate region selection */

drivers/staging/brcm80211/brcmsmac/pmu.c

@@ -139,7 +139,7 @@ static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
 }
 
 static void
-si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs *cc,
+si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc,
 			   u8 spuravoid)
 {
 	u32 tmp = 0;
@@ -221,7 +221,7 @@ u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
 
 void si_pmu_sprom_enable(struct si_pub *sih, bool enable)
 {
-	struct chipcregs *cc;
+	struct chipcregs __iomem *cc;
 	uint origidx;
 
 	/* Remember original core before switch to chipc */
@@ -294,11 +294,11 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
 
 void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
 {
-	struct chipcregs *cc;
+	struct chipcregs __iomem *cc;
 	uint origidx, intr_val;
 
 	/* Remember original core before switch to chipc */
-	cc = (struct chipcregs *)
+	cc = (struct chipcregs __iomem *)
 			ai_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
 
 	/* update the pll changes */
@@ -311,7 +311,7 @@ void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
 /* initialize PMU */
 void si_pmu_init(struct si_pub *sih)
 {
-	struct chipcregs *cc;
+	struct chipcregs __iomem *cc;
 	uint origidx;
 
 	/* Remember original core before switch to chipc */
@@ -350,7 +350,7 @@ void si_pmu_swreg_init(struct si_pub *sih)
 /* initialize PLL */
 void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
 {
-	struct chipcregs *cc;
+	struct chipcregs __iomem *cc;
 	uint origidx;
 
 	/* Remember original core before switch to chipc */
@@ -374,7 +374,7 @@ void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
 /* initialize PMU resources */
 void si_pmu_res_init(struct si_pub *sih)
 {
-	struct chipcregs *cc;
+	struct chipcregs __iomem *cc;
 	uint origidx;
 	u32 min_mask = 0, max_mask = 0;
 
@@ -406,7 +406,7 @@ void si_pmu_res_init(struct si_pub *sih)
 
 u32 si_pmu_measure_alpclk(struct si_pub *sih)
 {
-	struct chipcregs *cc;
+	struct chipcregs __iomem *cc;
 	uint origidx;
 	u32 alp_khz;
 

drivers/staging/brcm80211/brcmsmac/srom.c

@@ -782,12 +782,14 @@ static const struct brcms_sromvar perpath_pci_sromvars[] = {
  * shared between devices. */
 static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
 
-static u16 *srom_window_address(struct si_pub *sih, u8 *curmap)
+static u16 __iomem *
+srom_window_address(struct si_pub *sih, u8 __iomem *curmap)
 {
 	if (sih->ccrev < 32)
-		return (u16 *)(curmap + PCI_BAR0_SPROM_OFFSET);
+		return (u16 __iomem *)(curmap + PCI_BAR0_SPROM_OFFSET);
 	if (sih->cccaps & CC_CAP_SROM)
-		return (u16 *)(curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP);
+		return (u16 __iomem *)
+		       (curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP);
 
 	return NULL;
 }
@@ -1032,7 +1034,7 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, struct brcms_varbuf *b)
  * Return 0 on success, nonzero on error.
  */
 static int
-sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
+sprom_read_pci(struct si_pub *sih, u16 __iomem *sprom, uint wordoff,
 	       u16 *buf, uint nwords, bool check_crc)
 {
 	int err = 0;
@@ -1131,10 +1133,11 @@ static int initvars_table(char *start, char *end,
  * Initialize nonvolatile variable table from sprom.
  * Return 0 on success, nonzero on error.
  */
-static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
-			     uint *count)
+static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap,
+			     char **vars, uint *count)
 {
-	u16 *srom, *sromwindow;
+	u16 *srom;
+	u16 __iomem *sromwindow;
 	u8 sromrev = 0;
 	u32 sr;
 	struct brcms_varbuf b;
@@ -1222,7 +1225,8 @@ static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
  * Initialize local vars from the right source for this platform.
  * Return 0 on success, nonzero on error.
  */
-int srom_var_init(struct si_pub *sih, void *curmap, char **vars, uint *count)
+int srom_var_init(struct si_pub *sih, void __iomem *curmap, char **vars,
+		  uint *count)
 {
 	uint len;
 

drivers/staging/brcm80211/brcmsmac/srom.h

@@ -20,7 +20,7 @@
 #include "types.h"
 
 /* Prototypes */
-extern int srom_var_init(struct si_pub *sih, void *curmap, char **vars,
+extern int srom_var_init(struct si_pub *sih, void __iomem *curmap, char **vars,
 			 uint *count);
 
 extern int srom_read(struct si_pub *sih, uint bus, void *curmap,