Commit 9d6eccb9 authored by Arnd Bergmann's avatar Arnd Bergmann

ARM: davinci: remove tnetv107x support

The tnetv107x support does not compile, and seems to have been broken
for a while with nobody caring to fix it. So far everyone I asked
said it's probably dead and completely unused and will never again
be needed in a future kernel release, so let's delete it.

If someone finds a use for this code later and is able to get it
to work again, we can always revert the removal.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarSekhar Nori <nsekhar@ti.com>
Acked-by: default avatarKevin Hilman <khilman@linaro.org>
parent a92177ea
......@@ -176,15 +176,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART0 serial port on DaVinci DMx devices.
config DEBUG_DAVINCI_TNETV107X_UART1
bool "Kernel low-level debugging on DaVinci TNETV107x using UART1"
depends on ARCH_DAVINCI_TNETV107X
select DEBUG_UART_8250
help
Say Y here if you want the debug print routines to direct
their output to UART1 serial port on DaVinci TNETV107X
devices.
config DEBUG_ZYNQ_UART0
bool "Kernel low-level debugging on Xilinx Zynq using UART0"
depends on ARCH_ZYNQ
......@@ -1019,7 +1010,6 @@ config DEBUG_UART_PHYS
default 0x02530c00 if DEBUG_KEYSTONE_UART0
default 0x02531000 if DEBUG_KEYSTONE_UART1
default 0x03010fe0 if ARCH_RPC
default 0x08108300 if DEBUG_DAVINCI_TNETV107X_UART1
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \
DEBUG_VEXPRESS_UART0_CA9
default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
......@@ -1117,7 +1107,6 @@ config DEBUG_UART_VIRT
default 0xfed12000 if ARCH_KIRKWOOD
default 0xfedc0000 if ARCH_EP93XX
default 0xfee003f8 if FOOTBRIDGE
default 0xfee08300 if DEBUG_DAVINCI_TNETV107X_UART1
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfee82340 if ARCH_IOP13XX
......@@ -1142,7 +1131,7 @@ config DEBUG_UART_8250_WORD
default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
ARCH_KEYSTONE || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || \
DEBUG_BCM_KONA_UART
config DEBUG_UART_8250_FLOW_CONTROL
......
......@@ -51,11 +51,6 @@ config ARCH_DAVINCI_DM365
select AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_TNETV107X
bool "TNETV107X based system"
select CPU_V6
select CP_INTC
comment "DaVinci Board Type"
config MACH_DA8XX_DT
......@@ -220,13 +215,6 @@ config GPIO_PCA953X
config KEYBOARD_GPIO_POLLED
default MACH_DAVINCI_DA850_EVM
config MACH_TNETV107X
bool "TI TNETV107X Reference Platform"
default ARCH_DAVINCI_TNETV107X
depends on ARCH_DAVINCI_TNETV107X
help
Say Y here to select the TI TNETV107X Evaluation Module.
config MACH_MITYOMAPL138
bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
depends on ARCH_DAVINCI_DA850
......
......@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o
obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o
obj-$(CONFIG_AINTC) += irq.o
obj-$(CONFIG_CP_INTC) += cp_intc.o
......@@ -32,7 +31,6 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o
obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o
obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o
obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o
......
/*
* Texas Instruments TNETV107X EVM Board Support
*
* Copyright (C) 2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/ratelimit.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <linux/platform_data/edma.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/irqs.h>
#include <mach/mux.h>
#include <mach/cp_intc.h>
#include <mach/tnetv107x.h>
#define EVM_MMC_WP_GPIO 21
#define EVM_MMC_CD_GPIO 24
#define EVM_SPI_CS_GPIO 54
static int initialize_gpio(int gpio, char *desc)
{
int ret;
ret = gpio_request(gpio, desc);
if (ret < 0) {
pr_err_ratelimited("cannot open %s gpio\n", desc);
return -ENOSYS;
}
gpio_direction_input(gpio);
return gpio;
}
static int mmc_get_cd(int index)
{
static int gpio;
if (!gpio)
gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
if (gpio < 0)
return gpio;
return gpio_get_value(gpio) ? 0 : 1;
}
static int mmc_get_ro(int index)
{
static int gpio;
if (!gpio)
gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
if (gpio < 0)
return gpio;
return gpio_get_value(gpio) ? 1 : 0;
}
static struct davinci_mmc_config mmc_config = {
.get_cd = mmc_get_cd,
.get_ro = mmc_get_ro,
.wires = 4,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
};
static const short sdio1_pins[] __initconst = {
TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1,
TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1,
TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1,
TNETV107X_GPIO21, TNETV107X_GPIO24,
-1
};
static const short uart1_pins[] __initconst = {
TNETV107X_UART1_RD, TNETV107X_UART1_TD,
-1
};
static const short ssp_pins[] __initconst = {
TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
TNETV107X_SSP1_3, -1
};
static struct mtd_partition nand_partitions[] = {
/* bootloader (U-Boot, etc) in first 12 sectors */
{
.name = "bootloader",
.offset = 0,
.size = (12*SZ_128K),
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* bootloader params in the next sector */
{
.name = "params",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* kernel */
{
.name = "kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_4M,
.mask_flags = 0,
},
/* file system */
{
.name = "filesystem",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
}
};
static struct davinci_nand_pdata nand_config = {
.mask_cle = 0x4000,
.mask_ale = 0x2000,
.parts = nand_partitions,
.nr_parts = ARRAY_SIZE(nand_partitions),
.ecc_mode = NAND_ECC_HW,
.bbt_options = NAND_BBT_USE_FLASH,
.ecc_bits = 1,
};
static struct davinci_uart_config serial_config __initconst = {
.enabled_uarts = BIT(1),
};
static const uint32_t keymap[] = {
KEY(0, 0, KEY_NUMERIC_1),
KEY(0, 1, KEY_NUMERIC_2),
KEY(0, 2, KEY_NUMERIC_3),
KEY(0, 3, KEY_FN_F1),
KEY(0, 4, KEY_MENU),
KEY(1, 0, KEY_NUMERIC_4),
KEY(1, 1, KEY_NUMERIC_5),
KEY(1, 2, KEY_NUMERIC_6),
KEY(1, 3, KEY_UP),
KEY(1, 4, KEY_FN_F2),
KEY(2, 0, KEY_NUMERIC_7),
KEY(2, 1, KEY_NUMERIC_8),
KEY(2, 2, KEY_NUMERIC_9),
KEY(2, 3, KEY_LEFT),
KEY(2, 4, KEY_ENTER),
KEY(3, 0, KEY_NUMERIC_STAR),
KEY(3, 1, KEY_NUMERIC_0),
KEY(3, 2, KEY_NUMERIC_POUND),
KEY(3, 3, KEY_DOWN),
KEY(3, 4, KEY_RIGHT),
KEY(4, 0, KEY_FN_F3),
KEY(4, 1, KEY_FN_F4),
KEY(4, 2, KEY_MUTE),
KEY(4, 3, KEY_HOME),
KEY(4, 4, KEY_BACK),
KEY(5, 0, KEY_VOLUMEDOWN),
KEY(5, 1, KEY_VOLUMEUP),
KEY(5, 2, KEY_F1),
KEY(5, 3, KEY_F2),
KEY(5, 4, KEY_F3),
};
static const struct matrix_keymap_data keymap_data = {
.keymap = keymap,
.keymap_size = ARRAY_SIZE(keymap),
};
static struct matrix_keypad_platform_data keypad_config = {
.keymap_data = &keymap_data,
.num_row_gpios = 6,
.num_col_gpios = 5,
.debounce_ms = 0, /* minimum */
.active_low = 0, /* pull up realization */
.no_autorepeat = 0,
};
static void spi_select_device(int cs)
{
static int gpio;
if (!gpio) {
int ret;
ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
if (ret < 0) {
pr_err("cannot open spi chipsel gpio\n");
gpio = -ENOSYS;
return;
} else {
gpio = EVM_SPI_CS_GPIO;
gpio_direction_output(gpio, 0);
}
}
if (gpio < 0)
return;
return gpio_set_value(gpio, cs ? 1 : 0);
}
static struct ti_ssp_spi_data spi_master_data = {
.num_cs = 2,
.select = spi_select_device,
.iosel = SSP_PIN_SEL(0, SSP_CLOCK) | SSP_PIN_SEL(1, SSP_DATA) |
SSP_PIN_SEL(2, SSP_CHIPSEL) | SSP_PIN_SEL(3, SSP_IN) |
SSP_INPUT_SEL(3),
};
static struct ti_ssp_data ssp_config = {
.out_clock = 250 * 1000,
.dev_data = {
[1] = {
.dev_name = "ti-ssp-spi",
.pdata = &spi_master_data,
.pdata_size = sizeof(spi_master_data),
},
},
};
static struct tnetv107x_device_info evm_device_info __initconst = {
.serial_config = &serial_config,
.mmc_config[1] = &mmc_config, /* controller 1 */
.nand_config[0] = &nand_config, /* chip select 0 */
.keypad_config = &keypad_config,
.ssp_config = &ssp_config,
};
static struct spi_board_info spi_info[] __initconst = {
};
static __init void tnetv107x_evm_board_init(void)
{
davinci_cfg_reg_list(sdio1_pins);
davinci_cfg_reg_list(uart1_pins);
davinci_cfg_reg_list(ssp_pins);
tnetv107x_devices_init(&evm_device_info);
spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init tnetv107x_evm_console_init(void)
{
return add_preferred_console("ttyS", 0, "115200");
}
console_initcall(tnetv107x_evm_console_init);
#endif
MACHINE_START(TNETV107X, "TNETV107X EVM")
.atag_offset = 0x100,
.map_io = tnetv107x_init,
.init_irq = cp_intc_init,
.init_time = davinci_timer_init,
.init_machine = tnetv107x_evm_board_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = tnetv107x_restart,
MACHINE_END
This diff is collapsed.
......@@ -33,7 +33,6 @@ struct davinci_id {
#define DAVINCI_CPU_ID_DM365 0x03650000
#define DAVINCI_CPU_ID_DA830 0x08300000
#define DAVINCI_CPU_ID_DA850 0x08500000
#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
#define IS_DAVINCI_CPU(type, id) \
static inline int is_davinci_ ##type(void) \
......@@ -47,7 +46,6 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
#ifdef CONFIG_ARCH_DAVINCI_DM644x
#define cpu_is_davinci_dm644x() is_davinci_dm644x()
......@@ -85,10 +83,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
#define cpu_is_davinci_da850() 0
#endif
#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
#else
#define cpu_is_davinci_tnetv107x() 0
#endif
#endif
......@@ -401,103 +401,6 @@
#define DA850_N_CP_INTC_IRQ 101
/* TNETV107X specific interrupts */
#define IRQ_TNETV107X_TDM1_TXDMA 0
#define IRQ_TNETV107X_EXT_INT_0 1
#define IRQ_TNETV107X_EXT_INT_1 2
#define IRQ_TNETV107X_GPIO_INT12 3
#define IRQ_TNETV107X_GPIO_INT13 4
#define IRQ_TNETV107X_TIMER_0_TINT12 5
#define IRQ_TNETV107X_TIMER_1_TINT12 6
#define IRQ_TNETV107X_UART0 7
#define IRQ_TNETV107X_TDM1_RXDMA 8
#define IRQ_TNETV107X_MCDMA_INT0 9
#define IRQ_TNETV107X_MCDMA_INT1 10
#define IRQ_TNETV107X_TPCC 11
#define IRQ_TNETV107X_TPCC_INT0 12
#define IRQ_TNETV107X_TPCC_INT1 13
#define IRQ_TNETV107X_TPCC_INT2 14
#define IRQ_TNETV107X_TPCC_INT3 15
#define IRQ_TNETV107X_TPTC0 16
#define IRQ_TNETV107X_TPTC1 17
#define IRQ_TNETV107X_TIMER_0_TINT34 18
#define IRQ_TNETV107X_ETHSS 19
#define IRQ_TNETV107X_TIMER_1_TINT34 20
#define IRQ_TNETV107X_DSP2ARM_INT0 21
#define IRQ_TNETV107X_DSP2ARM_INT1 22
#define IRQ_TNETV107X_ARM_NPMUIRQ 23
#define IRQ_TNETV107X_USB1 24
#define IRQ_TNETV107X_VLYNQ 25
#define IRQ_TNETV107X_UART0_DMATX 26
#define IRQ_TNETV107X_UART0_DMARX 27
#define IRQ_TNETV107X_TDM1_TXMCSP 28
#define IRQ_TNETV107X_SSP 29
#define IRQ_TNETV107X_MCDMA_INT2 30
#define IRQ_TNETV107X_MCDMA_INT3 31
#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
#define IRQ_TNETV107X_USB0 34
#define IRQ_TNETV107X_USB_CDMA 35
#define IRQ_TNETV107X_LCD 36
#define IRQ_TNETV107X_KEYPAD 37
#define IRQ_TNETV107X_KEYPAD_FREE 38
#define IRQ_TNETV107X_RNG 39
#define IRQ_TNETV107X_PKA 40
#define IRQ_TNETV107X_TDM0_TXDMA 41
#define IRQ_TNETV107X_TDM0_RXDMA 42
#define IRQ_TNETV107X_TDM0_TXMCSP 43
#define IRQ_TNETV107X_TDM0_RXMCSP 44
#define IRQ_TNETV107X_TDM1_RXMCSP 45
#define IRQ_TNETV107X_SDIO1 46
#define IRQ_TNETV107X_SDIO0 47
#define IRQ_TNETV107X_TSC 48
#define IRQ_TNETV107X_TS 49
#define IRQ_TNETV107X_UART1 50
#define IRQ_TNETV107X_MBX_LITE 51
#define IRQ_TNETV107X_GPIO_INT00 52
#define IRQ_TNETV107X_GPIO_INT01 53
#define IRQ_TNETV107X_GPIO_INT02 54
#define IRQ_TNETV107X_GPIO_INT03 55
#define IRQ_TNETV107X_UART2 56
#define IRQ_TNETV107X_UART2_DMATX 57
#define IRQ_TNETV107X_UART2_DMARX 58
#define IRQ_TNETV107X_IMCOP_IMX 59
#define IRQ_TNETV107X_IMCOP_VLCD 60
#define IRQ_TNETV107X_AES 61
#define IRQ_TNETV107X_DES 62
#define IRQ_TNETV107X_SHAMD5 63
#define IRQ_TNETV107X_TPCC_ERR 68
#define IRQ_TNETV107X_TPCC_PROT 69
#define IRQ_TNETV107X_TPTC0_ERR 70
#define IRQ_TNETV107X_TPTC1_ERR 71
#define IRQ_TNETV107X_UART0_ERR 72
#define IRQ_TNETV107X_UART1_ERR 73
#define IRQ_TNETV107X_AEMIF_ERR 74
#define IRQ_TNETV107X_DDR_ERR 75
#define IRQ_TNETV107X_WDTARM_INT0 76
#define IRQ_TNETV107X_MCDMA_ERR 77
#define IRQ_TNETV107X_GPIO_ERR 78
#define IRQ_TNETV107X_MPU_ADDR 79
#define IRQ_TNETV107X_MPU_PROT 80
#define IRQ_TNETV107X_IOPU_ADDR 81
#define IRQ_TNETV107X_IOPU_PROT 82
#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
#define IRQ_TNETV107X_PLL_UNLOCK 87
#define IRQ_TNETV107X_WDTDSP_INT0 88
#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
#define IRQ_TNETV107X_PBIST_CPU 91
#define IRQ_TNETV107X_WDTARM 92
#define IRQ_TNETV107X_PSC 93
#define IRQ_TNETV107X_MMC0 94
#define IRQ_TNETV107X_MMC1 95
#define TNETV107X_N_CP_INTC_IRQ 96
/* da850 currently has the most gpio pins (144) */
#define DAVINCI_N_GPIO 144
/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
......
......@@ -972,275 +972,6 @@ enum davinci_da850_index {
DA850_VPIF_CLKO3,
};
enum davinci_tnetv107x_index {
TNETV107X_ASR_A00,
TNETV107X_GPIO32,
TNETV107X_ASR_A01,
TNETV107X_GPIO33,
TNETV107X_ASR_A02,
TNETV107X_GPIO34,
TNETV107X_ASR_A03,
TNETV107X_GPIO35,
TNETV107X_ASR_A04,
TNETV107X_GPIO36,
TNETV107X_ASR_A05,
TNETV107X_GPIO37,
TNETV107X_ASR_A06,
TNETV107X_GPIO38,
TNETV107X_ASR_A07,
TNETV107X_GPIO39,
TNETV107X_ASR_A08,
TNETV107X_GPIO40,
TNETV107X_ASR_A09,
TNETV107X_GPIO41,
TNETV107X_ASR_A10,
TNETV107X_GPIO42,
TNETV107X_ASR_A11,
TNETV107X_BOOT_STRP_0,
TNETV107X_ASR_A12,
TNETV107X_BOOT_STRP_1,
TNETV107X_ASR_A13,
TNETV107X_GPIO43,
TNETV107X_ASR_A14,
TNETV107X_GPIO44,
TNETV107X_ASR_A15,
TNETV107X_GPIO45,
TNETV107X_ASR_A16,
TNETV107X_GPIO46,
TNETV107X_ASR_A17,
TNETV107X_GPIO47,
TNETV107X_ASR_A18,
TNETV107X_GPIO48,
TNETV107X_SDIO1_DATA3_0,
TNETV107X_ASR_A19,
TNETV107X_GPIO49,
TNETV107X_SDIO1_DATA2_0,
TNETV107X_ASR_A20,
TNETV107X_GPIO50,
TNETV107X_SDIO1_DATA1_0,
TNETV107X_ASR_A21,
TNETV107X_GPIO51,
TNETV107X_SDIO1_DATA0_0,
TNETV107X_ASR_A22,
TNETV107X_GPIO52,
TNETV107X_SDIO1_CMD_0,
TNETV107X_ASR_A23,
TNETV107X_GPIO53,
TNETV107X_SDIO1_CLK_0,
TNETV107X_ASR_BA_1,
TNETV107X_GPIO54,
TNETV107X_SYS_PLL_CLK,
TNETV107X_ASR_CS0,
TNETV107X_ASR_CS1,
TNETV107X_ASR_CS2,
TNETV107X_TDM_PLL_CLK,
TNETV107X_ASR_CS3,
TNETV107X_ETH_PHY_CLK,
TNETV107X_ASR_D00,
TNETV107X_GPIO55,
TNETV107X_ASR_D01,
TNETV107X_GPIO56,
TNETV107X_ASR_D02,
TNETV107X_GPIO57,
TNETV107X_ASR_D03,
TNETV107X_GPIO58,
TNETV107X_ASR_D04,
TNETV107X_GPIO59_0,
TNETV107X_ASR_D05,
TNETV107X_GPIO60_0,
TNETV107X_ASR_D06,
TNETV107X_GPIO61_0,
TNETV107X_ASR_D07,
TNETV107X_GPIO62_0,
TNETV107X_ASR_D08,
TNETV107X_GPIO63_0,
TNETV107X_ASR_D09,
TNETV107X_GPIO64_0,
TNETV107X_ASR_D10,
TNETV107X_SDIO1_DATA3_1,
TNETV107X_ASR_D11,
TNETV107X_SDIO1_DATA2_1,
TNETV107X_ASR_D12,
TNETV107X_SDIO1_DATA1_1,
TNETV107X_ASR_D13,
TNETV107X_SDIO1_DATA0_1,
TNETV107X_ASR_D14,
TNETV107X_SDIO1_CMD_1,
TNETV107X_ASR_D15,
TNETV107X_SDIO1_CLK_1,
TNETV107X_ASR_OE,
TNETV107X_BOOT_STRP_2,
TNETV107X_ASR_RNW,
TNETV107X_GPIO29_0,
TNETV107X_ASR_WAIT,
TNETV107X_GPIO30_0,
TNETV107X_ASR_WE,
TNETV107X_BOOT_STRP_3,
TNETV107X_ASR_WE_DQM0,
TNETV107X_GPIO31,
TNETV107X_LCD_PD17_0,
TNETV107X_ASR_WE_DQM1,
TNETV107X_ASR_BA0_0,
TNETV107X_VLYNQ_CLK,
TNETV107X_GPIO14,
TNETV107X_LCD_PD19_0,
TNETV107X_VLYNQ_RXD0,
TNETV107X_GPIO15,
TNETV107X_LCD_PD20_0,
TNETV107X_VLYNQ_RXD1,
TNETV107X_GPIO16,
TNETV107X_LCD_PD21_0,
TNETV107X_VLYNQ_TXD0,
TNETV107X_GPIO17,
TNETV107X_LCD_PD22_0,
TNETV107X_VLYNQ_TXD1,
TNETV107X_GPIO18,
TNETV107X_LCD_PD23_0,
TNETV107X_SDIO0_CLK,
TNETV107X_GPIO19,
TNETV107X_SDIO0_CMD,
TNETV107X_GPIO20,
TNETV107X_SDIO0_DATA0,
TNETV107X_GPIO21,
TNETV107X_SDIO0_DATA1,
TNETV107X_GPIO22,
TNETV107X_SDIO0_DATA2,
TNETV107X_GPIO23,
TNETV107X_SDIO0_DATA3,
TNETV107X_GPIO24,
TNETV107X_EMU0,
TNETV107X_EMU1,
TNETV107X_RTCK,
TNETV107X_TRST_N,
TNETV107X_TCK,
TNETV107X_TDI,
TNETV107X_TDO,
TNETV107X_TMS,
TNETV107X_TDM1_CLK,
TNETV107X_TDM1_RX,
TNETV107X_TDM1_TX,
TNETV107X_TDM1_FS,
TNETV107X_KEYPAD_R0,
TNETV107X_KEYPAD_R1,
TNETV107X_KEYPAD_R2,
TNETV107X_KEYPAD_R3,
TNETV107X_KEYPAD_R4,
TNETV107X_KEYPAD_R5,
TNETV107X_KEYPAD_R6,
TNETV107X_GPIO12,
TNETV107X_KEYPAD_R7,
TNETV107X_GPIO10,
TNETV107X_KEYPAD_C0,
TNETV107X_KEYPAD_C1,
TNETV107X_KEYPAD_C2,
TNETV107X_KEYPAD_C3,
TNETV107X_KEYPAD_C4,
TNETV107X_KEYPAD_C5,
TNETV107X_KEYPAD_C6,
TNETV107X_GPIO13,
TNETV107X_TEST_CLK_IN,
TNETV107X_KEYPAD_C7,
TNETV107X_GPIO11,
TNETV107X_SSP0_0,
TNETV107X_SCC_DCLK,
TNETV107X_LCD_PD20_1,
TNETV107X_SSP0_1,
TNETV107X_SCC_CS_N,
TNETV107X_LCD_PD21_1,
TNETV107X_SSP0_2,
TNETV107X_SCC_D,
TNETV107X_LCD_PD22_1,
TNETV107X_SSP0_3,
TNETV107X_SCC_RESETN,
TNETV107X_LCD_PD23_1,
TNETV107X_SSP1_0,
TNETV107X_GPIO25,
TNETV107X_UART2_CTS,
TNETV107X_SSP1_1,
TNETV107X_GPIO26,
TNETV107X_UART2_RD,
TNETV107X_SSP1_2,
TNETV107X_GPIO27,
TNETV107X_UART2_RTS,
TNETV107X_SSP1_3,
TNETV107X_GPIO28,
TNETV107X_UART2_TD,
TNETV107X_UART0_CTS,
TNETV107X_UART0_RD,
TNETV107X_UART0_RTS,
TNETV107X_UART0_TD,
TNETV107X_UART1_RD,
TNETV107X_UART1_TD,
TNETV107X_LCD_AC_NCS,
TNETV107X_LCD_HSYNC_RNW,
TNETV107X_LCD_VSYNC_A0,
TNETV107X_LCD_MCLK,
TNETV107X_LCD_PD16_0,
TNETV107X_LCD_PCLK_E,
TNETV107X_LCD_PD00,
TNETV107X_LCD_PD01,
TNETV107X_LCD_PD02,
TNETV107X_LCD_PD03,
TNETV107X_LCD_PD04,
TNETV107X_LCD_PD05,
TNETV107X_LCD_PD06,
TNETV107X_LCD_PD07,
TNETV107X_LCD_PD08,
TNETV107X_GPIO59_1,
TNETV107X_LCD_PD09,
TNETV107X_GPIO60_1,
TNETV107X_LCD_PD10,
TNETV107X_ASR_BA0_1,
TNETV107X_GPIO61_1,
TNETV107X_LCD_PD11,
TNETV107X_GPIO62_1,
TNETV107X_LCD_PD12,
TNETV107X_GPIO63_1,
TNETV107X_LCD_PD13,
TNETV107X_GPIO64_1,
TNETV107X_LCD_PD14,
TNETV107X_GPIO29_1,
TNETV107X_LCD_PD15,
TNETV107X_GPIO30_1,
TNETV107X_EINT0,
TNETV107X_GPIO08,
TNETV107X_EINT1,
TNETV107X_GPIO09,
TNETV107X_GPIO00,
TNETV107X_LCD_PD20_2,
TNETV107X_TDM_CLK_IN_2,
TNETV107X_GPIO01,
TNETV107X_LCD_PD21_2,
TNETV107X_24M_CLK_OUT_1,
TNETV107X_GPIO02,
TNETV107X_LCD_PD22_2,
TNETV107X_GPIO03,
TNETV107X_LCD_PD23_2,
TNETV107X_GPIO04,
TNETV107X_LCD_PD16_1,
TNETV107X_USB0_RXERR,
TNETV107X_GPIO05,
TNETV107X_LCD_PD17_1,
TNETV107X_TDM_CLK_IN_1,
TNETV107X_GPIO06,
TNETV107X_LCD_PD18,
TNETV107X_24M_CLK_OUT_2,
TNETV107X_GPIO07,
TNETV107X_LCD_PD19_1,
TNETV107X_USB1_RXERR,
TNETV107X_ETH_PLL_CLK,
TNETV107X_MDIO,
TNETV107X_MDC,
TNETV107X_AIC_MUTE_STAT_N,
TNETV107X_TDM0_CLK,
TNETV107X_AIC_HNS_EN_N,
TNETV107X_TDM0_FS,
TNETV107X_AIC_HDS_EN_STAT_N,
TNETV107X_TDM0_TX,
TNETV107X_AIC_HNF_EN_STAT_N,
TNETV107X_TDM0_RX,
};
#define PINMUX(x) (4 * (x))
#ifdef CONFIG_DAVINCI_MUX
......
......@@ -182,53 +182,6 @@
#define DA8XX_LPSC1_CR_P3_SS 26
#define DA8XX_LPSC1_L3_CBA_RAM 31
/* TNETV107X LPSC Assignments */
#define TNETV107X_LPSC_ARM 0
#define TNETV107X_LPSC_GEM 1
#define TNETV107X_LPSC_DDR2_PHY 2
#define TNETV107X_LPSC_TPCC 3
#define TNETV107X_LPSC_TPTC0 4
#define TNETV107X_LPSC_TPTC1 5
#define TNETV107X_LPSC_RAM 6
#define TNETV107X_LPSC_MBX_LITE 7
#define TNETV107X_LPSC_LCD 8
#define TNETV107X_LPSC_ETHSS 9
#define TNETV107X_LPSC_AEMIF 10
#define TNETV107X_LPSC_CHIP_CFG 11
#define TNETV107X_LPSC_TSC 12
#define TNETV107X_LPSC_ROM 13
#define TNETV107X_LPSC_UART2 14
#define TNETV107X_LPSC_PKTSEC 15
#define TNETV107X_LPSC_SECCTL 16
#define TNETV107X_LPSC_KEYMGR 17
#define TNETV107X_LPSC_KEYPAD 18
#define TNETV107X_LPSC_GPIO 19
#define TNETV107X_LPSC_MDIO 20
#define TNETV107X_LPSC_SDIO0 21
#define TNETV107X_LPSC_UART0 22
#define TNETV107X_LPSC_UART1 23
#define TNETV107X_LPSC_TIMER0 24
#define TNETV107X_LPSC_TIMER1 25
#define TNETV107X_LPSC_WDT_ARM 26
#define TNETV107X_LPSC_WDT_DSP 27
#define TNETV107X_LPSC_SSP 28
#define TNETV107X_LPSC_TDM0 29
#define TNETV107X_LPSC_VLYNQ 30
#define TNETV107X_LPSC_MCDMA 31
#define TNETV107X_LPSC_USB0 32
#define TNETV107X_LPSC_TDM1 33
#define TNETV107X_LPSC_DEBUGSS 34
#define TNETV107X_LPSC_ETHSS_RGMII 35
#define TNETV107X_LPSC_SYSTEM 36
#define TNETV107X_LPSC_IMCOP 37
#define TNETV107X_LPSC_SPARE 38
#define TNETV107X_LPSC_SDIO1 39
#define TNETV107X_LPSC_USB1 40
#define TNETV107X_LPSC_USBSS 41
#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
#define TNETV107X_LPSC_MAX 44
/* PSC register offsets */
#define EPCPR 0x070
#define PTCMD 0x120
......
......@@ -23,14 +23,6 @@
#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
#define TNETV107X_UART0_BASE 0x08108100
#define TNETV107X_UART1_BASE 0x08088400
#define TNETV107X_UART2_BASE 0x08108300
#define TNETV107X_UART0_VIRT IOMEM(0xfee08100)
#define TNETV107X_UART1_VIRT IOMEM(0xfed88400)
#define TNETV107X_UART2_VIRT IOMEM(0xfee08300)
/* DaVinci UART register offsets */
#define UART_DAVINCI_PWREMU 0x0c
#define UART_DM646X_SCR 0x10
......
/*
* Texas Instruments TNETV107X SoC Specific Defines
*
* Copyright (C) 2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
#define __ASM_ARCH_DAVINCI_TNETV107X_H
#include <asm/sizes.h>
#define TNETV107X_DDR_BASE 0x80000000
/*
* Fixed mapping for early init starts here. If low-level debug is enabled,
* this area also gets mapped via io_pg_offset and io_phys by the boot code.
* To fit in with the io_pg_offset calculation, the io base address selected
* here _must_ be a multiple of 2^20.
*/
#define TNETV107X_IO_BASE 0x08000000
#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M)
#define TNETV107X_N_GPIO 65
#ifndef __ASSEMBLY__
#include <linux/serial_8250.h>
#include <linux/input/matrix_keypad.h>
#include <linux/mfd/ti_ssp.h>
#include <linux/reboot.h>
#include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <mach/serial.h>
struct tnetv107x_device_info {
struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
struct matrix_keypad_platform_data *keypad_config;
struct ti_ssp_data *ssp_config;
};
extern struct platform_device tnetv107x_wdt_device;
extern struct platform_device tnetv107x_serial_device[];
extern void tnetv107x_init(void);
extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
extern void tnetv107x_irq_init(void);
void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
#endif
#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
......@@ -68,9 +68,6 @@ static inline void set_uart_info(u32 phys)
#define DEBUG_LL_DA8XX(machine, port) \
_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
#define DEBUG_LL_TNETV107X(machine, port) \
_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
static inline void __arch_decomp_setup(unsigned long arch_id)
{
/*
......@@ -94,9 +91,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_DA8XX(davinci_da850_evm, 2);
DEBUG_LL_DA8XX(mityomapl138, 1);
DEBUG_LL_DA8XX(omapl138_hawkboard, 2);
/* TNETV107x boards */
DEBUG_LL_TNETV107X(tnetv107x, 1);
} while (0);
}
......
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