Commit 9ddebc46 authored by David Daney's avatar David Daney Committed by Ralf Baechle

MIPS: OCTEON: Rename Kconfig CAVIUM_OCTEON_REFERENCE_BOARD to CAVIUM_OCTEON_SOC

CAVIUM_OCTEON_SOC most place we used to use CPU_CAVIUM_OCTEON.  This
allows us to CPU_CAVIUM_OCTEON in places where we have no OCTEON SOC.

Remove CAVIUM_OCTEON_SIMULATOR as it doesn't really do anything, we can
get the same configuration with CAVIUM_OCTEON_SOC.
Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-ide@vger.kernel.org
Cc: linux-edac@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: spi-devel-general@lists.sourceforge.net
Cc: devel@driverdev.osuosl.org
Cc: linux-usb@vger.kernel.org
Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: default avatarWolfram Sang <wsa@the-dreams.de>
Acked-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
Patchwork: https://patchwork.linux-mips.org/patch/5295/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 6e7582bf
...@@ -735,23 +735,8 @@ config WR_PPMC ...@@ -735,23 +735,8 @@ config WR_PPMC
This enables support for the Wind River MIPS32 4KC PPMC evaluation This enables support for the Wind River MIPS32 4KC PPMC evaluation
board, which is based on GT64120 bridge chip. board, which is based on GT64120 bridge chip.
config CAVIUM_OCTEON_SIMULATOR config CAVIUM_OCTEON_SOC
bool "Cavium Networks Octeon Simulator" bool "Cavium Networks Octeon SoC based boards"
select CEVT_R4K
select 64BIT_PHYS_ADDR
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HOTPLUG_CPU
select SYS_HAS_CPU_CAVIUM_OCTEON
select HOLES_IN_ZONE
help
The Octeon simulator is software performance model of the Cavium
Octeon Processor. It supports simulating Octeon processors on x86
hardware.
config CAVIUM_OCTEON_REFERENCE_BOARD
bool "Cavium Networks Octeon reference board"
select CEVT_R4K select CEVT_R4K
select 64BIT_PHYS_ADDR select 64BIT_PHYS_ADDR
select DMA_COHERENT select DMA_COHERENT
......
...@@ -10,6 +10,10 @@ config CAVIUM_CN63XXP1 ...@@ -10,6 +10,10 @@ config CAVIUM_CN63XXP1
non-CN63XXP1 hardware, so it is recommended to select "n" non-CN63XXP1 hardware, so it is recommended to select "n"
unless it is known the workarounds are needed. unless it is known the workarounds are needed.
endif # CPU_CAVIUM_OCTEON
if CAVIUM_OCTEON_SOC
config CAVIUM_OCTEON_2ND_KERNEL config CAVIUM_OCTEON_2ND_KERNEL
bool "Build the kernel to be used as a 2nd kernel on the same chip" bool "Build the kernel to be used as a 2nd kernel on the same chip"
default "n" default "n"
...@@ -103,4 +107,4 @@ config OCTEON_ILM ...@@ -103,4 +107,4 @@ config OCTEON_ILM
To compile this driver as a module, choose M here. The module To compile this driver as a module, choose M here. The module
will be called octeon-ilm will be called octeon-ilm
endif # CPU_CAVIUM_OCTEON endif # CAVIUM_OCTEON_SOC
# #
# Cavium Octeon # Cavium Octeon
# #
platform-$(CONFIG_CPU_CAVIUM_OCTEON) += cavium-octeon/ platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += \ cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \
-I$(srctree)/arch/mips/include/asm/mach-cavium-octeon -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000 load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000
else else
load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000 load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000
endif endif
CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y CONFIG_CAVIUM_OCTEON_SOC=y
CONFIG_CAVIUM_CN63XXP1=y CONFIG_CAVIUM_CN63XXP1=y
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM_MANUAL=y
......
...@@ -54,10 +54,10 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o ...@@ -54,10 +54,10 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o
obj-$(CONFIG_CPU_XLR) += pci-xlr.o obj-$(CONFIG_CPU_XLR) += pci-xlr.o
obj-$(CONFIG_CPU_XLP) += pci-xlp.o obj-$(CONFIG_CPU_XLP) += pci-xlp.o
ifdef CONFIG_PCI_MSI ifdef CONFIG_PCI_MSI
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o
endif endif
...@@ -160,7 +160,7 @@ config PDC_ADMA ...@@ -160,7 +160,7 @@ config PDC_ADMA
config PATA_OCTEON_CF config PATA_OCTEON_CF
tristate "OCTEON Boot Bus Compact Flash support" tristate "OCTEON Boot Bus Compact Flash support"
depends on CPU_CAVIUM_OCTEON depends on CAVIUM_OCTEON_SOC
help help
This option enables a polled compact flash driver for use with This option enables a polled compact flash driver for use with
compact flash cards attached to the OCTEON boot bus. compact flash cards attached to the OCTEON boot bus.
......
...@@ -167,7 +167,7 @@ config HW_RANDOM_OMAP ...@@ -167,7 +167,7 @@ config HW_RANDOM_OMAP
config HW_RANDOM_OCTEON config HW_RANDOM_OCTEON
tristate "Octeon Random Number Generator support" tristate "Octeon Random Number Generator support"
depends on HW_RANDOM && CPU_CAVIUM_OCTEON depends on HW_RANDOM && CAVIUM_OCTEON_SOC
default HW_RANDOM default HW_RANDOM
---help--- ---help---
This driver provides kernel-side support for the Random Number This driver provides kernel-side support for the Random Number
......
...@@ -349,21 +349,21 @@ config EDAC_OCTEON_PC ...@@ -349,21 +349,21 @@ config EDAC_OCTEON_PC
config EDAC_OCTEON_L2C config EDAC_OCTEON_L2C
tristate "Cavium Octeon Secondary Caches (L2C)" tristate "Cavium Octeon Secondary Caches (L2C)"
depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
help help
Support for error detection and correction on the Support for error detection and correction on the
Cavium Octeon family of SOCs. Cavium Octeon family of SOCs.
config EDAC_OCTEON_LMC config EDAC_OCTEON_LMC
tristate "Cavium Octeon DRAM Memory Controller (LMC)" tristate "Cavium Octeon DRAM Memory Controller (LMC)"
depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
help help
Support for error detection and correction on the Support for error detection and correction on the
Cavium Octeon family of SOCs. Cavium Octeon family of SOCs.
config EDAC_OCTEON_PCI config EDAC_OCTEON_PCI
tristate "Cavium Octeon PCI Controller" tristate "Cavium Octeon PCI Controller"
depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
help help
Support for error detection and correction on the Support for error detection and correction on the
Cavium Octeon family of SOCs. Cavium Octeon family of SOCs.
......
...@@ -726,7 +726,7 @@ config I2C_VERSATILE ...@@ -726,7 +726,7 @@ config I2C_VERSATILE
config I2C_OCTEON config I2C_OCTEON
tristate "Cavium OCTEON I2C bus support" tristate "Cavium OCTEON I2C bus support"
depends on CPU_CAVIUM_OCTEON depends on CAVIUM_OCTEON_SOC
help help
Say yes if you want to support the I2C serial bus on Cavium Say yes if you want to support the I2C serial bus on Cavium
OCTEON SOC. OCTEON SOC.
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
config OCTEON_MGMT_ETHERNET config OCTEON_MGMT_ETHERNET
tristate "Octeon Management port ethernet driver (CN5XXX, CN6XXX)" tristate "Octeon Management port ethernet driver (CN5XXX, CN6XXX)"
depends on CPU_CAVIUM_OCTEON depends on CAVIUM_OCTEON_SOC
select PHYLIB select PHYLIB
select MDIO_OCTEON select MDIO_OCTEON
default y default y
......
...@@ -135,7 +135,7 @@ config MDIO_GPIO ...@@ -135,7 +135,7 @@ config MDIO_GPIO
config MDIO_OCTEON config MDIO_OCTEON
tristate "Support for MDIO buses on Octeon SOCs" tristate "Support for MDIO buses on Octeon SOCs"
depends on CPU_CAVIUM_OCTEON depends on CAVIUM_OCTEON_SOC
default y default y
help help
......
...@@ -266,7 +266,7 @@ config SPI_OC_TINY ...@@ -266,7 +266,7 @@ config SPI_OC_TINY
config SPI_OCTEON config SPI_OCTEON
tristate "Cavium OCTEON SPI controller" tristate "Cavium OCTEON SPI controller"
depends on CPU_CAVIUM_OCTEON depends on CAVIUM_OCTEON_SOC
help help
SPI host driver for the hardware found on some Cavium OCTEON SPI host driver for the hardware found on some Cavium OCTEON
SOCs. SOCs.
......
config OCTEON_ETHERNET config OCTEON_ETHERNET
tristate "Cavium Networks Octeon Ethernet support" tristate "Cavium Networks Octeon Ethernet support"
depends on CPU_CAVIUM_OCTEON && NETDEVICES depends on CAVIUM_OCTEON_SOC && NETDEVICES
select PHYLIB select PHYLIB
select MDIO_OCTEON select MDIO_OCTEON
help help
......
...@@ -285,7 +285,7 @@ config USB_EHCI_HCD_PLATFORM ...@@ -285,7 +285,7 @@ config USB_EHCI_HCD_PLATFORM
config USB_OCTEON_EHCI config USB_OCTEON_EHCI
bool "Octeon on-chip EHCI support" bool "Octeon on-chip EHCI support"
depends on CPU_CAVIUM_OCTEON depends on CAVIUM_OCTEON_SOC
default n default n
select USB_EHCI_BIG_ENDIAN_MMIO select USB_EHCI_BIG_ENDIAN_MMIO
help help
...@@ -480,7 +480,7 @@ config USB_OHCI_HCD_PLATFORM ...@@ -480,7 +480,7 @@ config USB_OHCI_HCD_PLATFORM
config USB_OCTEON_OHCI config USB_OCTEON_OHCI
bool "Octeon on-chip OHCI support" bool "Octeon on-chip OHCI support"
depends on CPU_CAVIUM_OCTEON depends on CAVIUM_OCTEON_SOC
default USB_OCTEON_EHCI default USB_OCTEON_EHCI
select USB_OHCI_BIG_ENDIAN_MMIO select USB_OHCI_BIG_ENDIAN_MMIO
select USB_OHCI_LITTLE_ENDIAN select USB_OHCI_LITTLE_ENDIAN
......
...@@ -1072,7 +1072,7 @@ config TXX9_WDT ...@@ -1072,7 +1072,7 @@ config TXX9_WDT
config OCTEON_WDT config OCTEON_WDT
tristate "Cavium OCTEON SOC family Watchdog Timer" tristate "Cavium OCTEON SOC family Watchdog Timer"
depends on CPU_CAVIUM_OCTEON depends on CAVIUM_OCTEON_SOC
default y default y
select EXPORT_UASM if OCTEON_WDT = m select EXPORT_UASM if OCTEON_WDT = m
help help
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment