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Commit 9eb20074 authored by Linus Torvalds's avatar Linus Torvalds
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Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6 

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6:
  sh: SH-4A UBC support
  sh: interrupt exception handling rework
  sh: Default enable R7780RP IRQs.
  sh: Zero-out coherent buffer in consistent_alloc().
  sh: Convert IPR-IRQ to IRQ chip.
  sh: Convert INTC2 IRQ handler to irq_chip.
  sh: Fix pr_debug statements for sh4
  sh: Convert r7780rp IRQ handler to IRQ chip.
  sh: Updates for IRQ handler changes.
  sh: Kill off timer_ops get_frequency().
  sh: First step at generic timeofday support.
parents 8770c018 8ae91b9a
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Showing with 249 additions and 1100 deletions
arch/sh/Kconfig
View file @ 9eb20074
......@@ -45,6 +45,9 @@ config GENERIC_CALIBRATE_DELAY
config GENERIC_IOMAP
bool
config GENERIC_TIME
def_bool n
config ARCH_MAY_HAVE_PC_FDC
bool
......@@ -357,6 +360,7 @@ config CPU_HAS_SR_RB
endmenu
menu "Timer support"
depends on !GENERIC_TIME
config SH_TMU
bool "TMU timer support"
......
arch/sh/boards/hp6xx/hp6xx_apm.c
View file @ 9eb20074
......@@ -83,7 +83,7 @@ static int hp6x0_apm_get_info(char *buf, char **start, off_t fpos, int length)
return p - buf;
}
static irqreturn_t hp6x0_apm_interrupt(int irq, void *dev, struct pt_regs *regs)
static irqreturn_t hp6x0_apm_interrupt(int irq, void *dev)
{
if (!apm_suspended)
apm_queue_event(APM_USER_SUSPEND);
......@@ -96,7 +96,7 @@ static int __init hp6x0_apm_init(void)
int ret;
ret = request_irq(HP680_BTN_IRQ, hp6x0_apm_interrupt,
SA_INTERRUPT, MODNAME, 0);
IRQF_DISABLED, MODNAME, 0);
if (unlikely(ret < 0)) {
printk(KERN_ERR MODNAME ": IRQ %d request failed\n",
HP680_BTN_IRQ);
......
arch/sh/boards/landisk/landisk_pwb.c
View file @ 9eb20074
......@@ -135,7 +135,7 @@ static int swdrv_write(struct file *filp, const char *buff, size_t count,
return count;
}
static irqreturn_t sw_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t sw_interrupt(int irq, void *dev_id)
{
landisk_btn = (0x0ff & (~ctrl_inb(PA_STATUS)));
disable_irq(IRQ_BUTTON);
......
arch/sh/boards/mpc1211/setup.c
View file @ 9eb20074
......@@ -69,7 +69,6 @@ static void __init pci_write_config(unsigned long busNo,
static unsigned char m_irq_mask = 0xfb;
static unsigned char s_irq_mask = 0xff;
volatile unsigned long irq_err_count;
static void disable_mpc1211_irq(unsigned int irq)
{
......@@ -118,7 +117,7 @@ static void mask_and_ack_mpc1211(unsigned int irq)
if(irq < 8) {
if(m_irq_mask & (1<<irq)){
if(!mpc1211_irq_real(irq)){
irq_err_count++;
atomic_inc(&irq_err_count)
printk("spurious 8259A interrupt: IRQ %x\n",irq);
}
} else {
......@@ -131,7 +130,7 @@ static void mask_and_ack_mpc1211(unsigned int irq)
} else {
if(s_irq_mask & (1<<(irq - 8))){
if(!mpc1211_irq_real(irq)){
irq_err_count++;
atomic_inc(&irq_err_count);
printk("spurious 8259A interrupt: IRQ %x\n",irq);
}
} else {
......
arch/sh/boards/renesas/r7780rp/irq.c
View file @ 9eb20074
/*
* linux/arch/sh/boards/renesas/r7780rp/irq.c
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Renesas Solutions Highlander R7780RP-1 Support.
*
* Modified for R7780RP-1 by
* Atom Create Engineering Co., Ltd. 2002.
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2006 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/r7780rp/r7780rp.h>
#ifdef CONFIG_SH_R7780MP
static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
......@@ -20,71 +18,26 @@ static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
static int mask_pos[] = {15, 14, 13, 12, 11, 10, 9, 8, 7, 5, 6, 4, 0, 1, 2, 0};
#endif
static void enable_r7780rp_irq(unsigned int irq);
static void disable_r7780rp_irq(unsigned int irq);
/* shutdown is same as "disable" */
#define shutdown_r7780rp_irq disable_r7780rp_irq
static void ack_r7780rp_irq(unsigned int irq);
static void end_r7780rp_irq(unsigned int irq);
static unsigned int startup_r7780rp_irq(unsigned int irq)
{
enable_r7780rp_irq(irq);
return 0; /* never anything pending */
}
static void disable_r7780rp_irq(unsigned int irq)
{
unsigned short val;
unsigned short mask = 0xffff ^ (0x0001 << mask_pos[irq]);
/* Set the priority in IPR to 0 */
val = ctrl_inw(IRLCNTR1);
val &= mask;
ctrl_outw(val, IRLCNTR1);
}
static void enable_r7780rp_irq(unsigned int irq)
{
unsigned short val;
unsigned short value = (0x0001 << mask_pos[irq]);
/* Set priority in IPR back to original value */
val = ctrl_inw(IRLCNTR1);
val |= value;
ctrl_outw(val, IRLCNTR1);
}
static void ack_r7780rp_irq(unsigned int irq)
{
disable_r7780rp_irq(irq);
ctrl_outw(ctrl_inw(IRLCNTR1) | (1 << mask_pos[irq]), IRLCNTR1);
}
static void end_r7780rp_irq(unsigned int irq)
static void disable_r7780rp_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_r7780rp_irq(irq);
/* Set the priority in IPR to 0 */
ctrl_outw(ctrl_inw(IRLCNTR1) & (0xffff ^ (1 << mask_pos[irq])),
IRLCNTR1);
}
static struct hw_interrupt_type r7780rp_irq_type = {
.typename = "R7780RP-IRQ",
.startup = startup_r7780rp_irq,
.shutdown = shutdown_r7780rp_irq,
.enable = enable_r7780rp_irq,
.disable = disable_r7780rp_irq,
.ack = ack_r7780rp_irq,
.end = end_r7780rp_irq,
static struct irq_chip r7780rp_irq_chip __read_mostly = {
.name = "r7780rp",
.mask = disable_r7780rp_irq,
.unmask = enable_r7780rp_irq,
.mask_ack = disable_r7780rp_irq,
};
static void make_r7780rp_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_desc[irq].chip = &r7780rp_irq_type;
disable_r7780rp_irq(irq);
}
/*
* Initialize IRQ setting
*/
......@@ -92,24 +45,10 @@ void __init init_r7780rp_IRQ(void)
{
int i;
/* IRL0=PCI Slot #A
* IRL1=PCI Slot #B
* IRL2=PCI Slot #C
* IRL3=PCI Slot #D
* IRL4=CF Card
* IRL5=CF Card Insert
* IRL6=M66596
* IRL7=SD Card
* IRL8=Touch Panel
* IRL9=SCI
* IRL10=Serial
* IRL11=Extention #A
* IRL11=Extention #B
* IRL12=Debug LAN
* IRL13=Push Switch
* IRL14=ZiggBee IO
*/
for (i=0; i<15; i++)
make_r7780rp_irq(i);
for (i = 0; i < 15; i++) {
disable_irq_nosync(i);
set_irq_chip_and_handler(i, &r7780rp_irq_chip,
handle_level_irq);
enable_r7780rp_irq(i);
}
}
arch/sh/boards/snapgear/setup.c
View file @ 9eb20074
......@@ -33,7 +33,7 @@ extern void pcibios_init(void);
* EraseConfig handling functions
*/
static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
{
volatile char dummy __attribute__((unused)) = * (volatile char *) 0xb8000000;
......
arch/sh/cchips/hd6446x/hd64461/setup.c
View file @ 9eb20074
......@@ -71,7 +71,7 @@ static struct hw_interrupt_type hd64461_irq_type = {
.end = end_hd64461_irq,
};
static irqreturn_t hd64461_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t hd64461_interrupt(int irq, void *dev_id)
{
printk(KERN_INFO
"HD64461: spurious interrupt, nirr: 0x%x nimr: 0x%x\n",
......
arch/sh/cchips/hd6446x/hd64465/gpio.c
View file @ 9eb20074
......@@ -85,7 +85,7 @@ static struct {
void *dev;
} handlers[GPIO_NPORTS * 8];
static irqreturn_t hd64465_gpio_interrupt(int irq, void *dev, struct pt_regs *regs)
static irqreturn_t hd64465_gpio_interrupt(int irq, void *dev)
{
unsigned short port, pin, isr, mask, portpin;
......
arch/sh/cchips/hd6446x/hd64465/setup.c
View file @ 9eb20074
......@@ -84,7 +84,7 @@ static struct hw_interrupt_type hd64465_irq_type = {
};
static irqreturn_t hd64465_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t hd64465_interrupt(int irq, void *dev_id)
{
printk(KERN_INFO
"HD64465: spurious interrupt, nirr: 0x%x nimr: 0x%x\n",
......
arch/sh/cchips/voyagergx/irq.c
View file @ 9eb20074
......@@ -88,8 +88,7 @@ static struct hw_interrupt_type voyagergx_irq_type = {
.end = end_voyagergx_irq,
};
static irqreturn_t voyagergx_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
static irqreturn_t voyagergx_interrupt(int irq, void *dev_id)
{
printk(KERN_INFO
"VoyagerGX: spurious interrupt, status: 0x%x\n",
......
arch/sh/drivers/dma/dma-g2.c
View file @ 9eb20074
......@@ -51,7 +51,7 @@ static volatile struct g2_dma_info *g2_dma = (volatile struct g2_dma_info *)0xa0
((g2_dma->channel[i].size - \
g2_dma->status[i].size) & 0x0fffffff)
static irqreturn_t g2_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t g2_dma_interrupt(int irq, void *dev_id)
{
int i;
......
arch/sh/drivers/dma/dma-pvr2.c
View file @ 9eb20074
......@@ -21,7 +21,7 @@
static unsigned int xfer_complete;
static int count;
static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
{
if (get_dma_residue(PVR2_CASCADE_CHAN)) {
printk(KERN_WARNING "DMA: SH DMAC did not complete transfer "
......
arch/sh/drivers/dma/dma-sh.c
View file @ 9eb20074
......@@ -60,9 +60,9 @@ static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
* Besides that it needs to waken any waiting process, which should handle
* setting up the next transfer.
*/
static irqreturn_t dma_tei(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t dma_tei(int irq, void *dev_id)
{
struct dma_channel *chan = (struct dma_channel *)dev_id;
struct dma_channel *chan = dev_id;
u32 chcr;
chcr = ctrl_inl(CHCR[chan->chan]);
......@@ -228,7 +228,7 @@ static inline int dmaor_reset(void)
}
#if defined(CONFIG_CPU_SH4)
static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t dma_err(int irq, void *dummy)
{
dmaor_reset();
disable_irq(irq);
......
arch/sh/drivers/pci/pci-sh7751.c
View file @ 9eb20074
......@@ -155,7 +155,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
*/
pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
PCIBIOS_MIN_IO, (64 << 10),
SH4_PCI_IO_BASE + PCIBIOS_MIN_IO);
SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
/*
* XXX: For now, leave this board-specific. In the event we have other
......@@ -163,7 +163,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
*/
#ifdef CONFIG_SH_BIGSUR
bigsur_port_map(PCIBIOS_MIN_IO, (64 << 10),
SH4_PCI_IO_BASE + PCIBIOS_MIN_IO, 0);
SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO, 0);
#endif
/* Make sure the MSB's of IO window are set to access PCI space
......
arch/sh/drivers/pci/pci-st40.c
View file @ 9eb20074
......@@ -161,7 +161,7 @@ static char * pci_commands[16]={
"Memory Write-and-Invalidate"
};
static irqreturn_t st40_pci_irq(int irq, void *dev_instance, struct pt_regs *regs)
static irqreturn_t st40_pci_irq(int irq, void *dev_instance)
{
unsigned pci_int, pci_air, pci_cir, pci_aint;
static int count=0;
......
arch/sh/kernel/cpu/irq/intc2.c
View file @ 9eb20074
......@@ -10,93 +10,32 @@
* These are the "new Hitachi style" interrupts, as present on the
* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/machvec.h>
struct intc2_data {
unsigned char msk_offset;
unsigned char msk_shift;
int (*clear_irq) (int);
};
static struct intc2_data intc2_data[NR_INTC2_IRQS];
static void enable_intc2_irq(unsigned int irq);
static void disable_intc2_irq(unsigned int irq);
/* shutdown is same as "disable" */
#define shutdown_intc2_irq disable_intc2_irq
static void mask_and_ack_intc2(unsigned int);
static void end_intc2_irq(unsigned int irq);
static unsigned int startup_intc2_irq(unsigned int irq)
{
enable_intc2_irq(irq);
return 0; /* never anything pending */
}
static struct hw_interrupt_type intc2_irq_type = {
.typename = "INTC2-IRQ",
.startup = startup_intc2_irq,
.shutdown = shutdown_intc2_irq,
.enable = enable_intc2_irq,
.disable = disable_intc2_irq,
.ack = mask_and_ack_intc2,
.end = end_intc2_irq
};
static void disable_intc2_irq(unsigned int irq)
{
int irq_offset = irq - INTC2_FIRST_IRQ;
int msk_shift, msk_offset;
/* Sanity check */
if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
return;
msk_shift = intc2_data[irq_offset].msk_shift;
msk_offset = intc2_data[irq_offset].msk_offset;
ctrl_outl(1 << msk_shift,
INTC2_BASE + INTC2_INTMSK_OFFSET + msk_offset);
struct intc2_data *p = get_irq_chip_data(irq);
ctrl_outl(1 << p->msk_shift,
INTC2_BASE + INTC2_INTMSK_OFFSET + p->msk_offset);
}
static void enable_intc2_irq(unsigned int irq)
{
int irq_offset = irq - INTC2_FIRST_IRQ;
int msk_shift, msk_offset;
/* Sanity check */
if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
return;
msk_shift = intc2_data[irq_offset].msk_shift;
msk_offset = intc2_data[irq_offset].msk_offset;
ctrl_outl(1 << msk_shift,
INTC2_BASE + INTC2_INTMSKCLR_OFFSET + msk_offset);
}
static void mask_and_ack_intc2(unsigned int irq)
{
disable_intc2_irq(irq);
struct intc2_data *p = get_irq_chip_data(irq);
ctrl_outl(1 << p->msk_shift,
INTC2_BASE + INTC2_INTMSKCLR_OFFSET + p->msk_offset);
}
static void end_intc2_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_intc2_irq(irq);
if (unlikely(intc2_data[irq - INTC2_FIRST_IRQ].clear_irq))
intc2_data[irq - INTC2_FIRST_IRQ].clear_irq(irq);
}
static struct irq_chip intc2_irq_chip = {
.typename = "intc2",
.mask = disable_intc2_irq,
.unmask = enable_intc2_irq,
.mask_ack = disable_intc2_irq,
};
/*
* Setup an INTC2 style interrupt.
......@@ -108,46 +47,30 @@ static void end_intc2_irq(unsigned int irq)
* | | | |
* make_intc2_irq(84, 0, 16, 0, 13);
*/
void make_intc2_irq(unsigned int irq,
unsigned int ipr_offset, unsigned int ipr_shift,
unsigned int msk_offset, unsigned int msk_shift,
unsigned int priority)
void make_intc2_irq(struct intc2_data *p)
{
int irq_offset = irq - INTC2_FIRST_IRQ;
unsigned int flags;
unsigned long ipr;
if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
return;
disable_irq_nosync(irq);
/* Fill the data we need */
intc2_data[irq_offset].msk_offset = msk_offset;
intc2_data[irq_offset].msk_shift = msk_shift;
intc2_data[irq_offset].clear_irq = NULL;
disable_irq_nosync(p->irq);
/* Set the priority level */
local_irq_save(flags);
ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);
ipr &= ~(0xf << ipr_shift);
ipr |= priority << ipr_shift;
ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);
ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
ipr &= ~(0xf << p->ipr_shift);
ipr |= p->priority << p->ipr_shift;
ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
local_irq_restore(flags);
irq_desc[irq].chip = &intc2_irq_type;
set_irq_chip_and_handler(p->irq, &intc2_irq_chip, handle_level_irq);
set_irq_chip_data(p->irq, p);
disable_intc2_irq(irq);
enable_intc2_irq(p->irq);
}
static struct intc2_init {
unsigned short irq;
unsigned char ipr_offset, ipr_shift;
unsigned char msk_offset, msk_shift;
unsigned char priority;
} intc2_init_data[] __initdata = {
static struct intc2_data intc2_irq_table[] = {
#if defined(CONFIG_CPU_SUBTYPE_ST40)
{64, 0, 0, 0, 0, 13}, /* PCI serr */
{65, 0, 4, 0, 1, 13}, /* PCI err */
......@@ -266,19 +189,6 @@ void __init init_IRQ_intc2(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(intc2_init_data); i++) {
struct intc2_init *p = intc2_init_data + i;
make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,
p-> msk_offset, p->msk_shift, p->priority);
}
}
/* Adds a termination callback to the interrupt */
void intc2_add_clear_irq(int irq, int (*fn)(int))
{
if (unlikely(irq < INTC2_FIRST_IRQ))
return;
intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;
for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++)
make_intc2_irq(intc2_irq_table + i);
}
arch/sh/kernel/cpu/irq/ipr.c
View file @ 9eb20074
/*
* arch/sh/kernel/cpu/irq/ipr.c
* Interrupt handling for IPR-based IRQ.
*
* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
* Copyright (C) 2000 Kazumoto Kojima
* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
*
* Interrupt handling for IPR-based IRQ.
* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
* Copyright (C) 2006 Paul Mundt
*
* Supported system:
* On-chip supporting modules (TMU, RTC, etc.).
......@@ -13,12 +12,13 @@
* Hitachi SolutionEngine external I/O:
* MS7709SE01, MS7709ASE01, and MS7750SE01
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/machvec.h>
......@@ -28,93 +28,45 @@ struct ipr_data {
int shift; /* Shifts of the 16-bit data */
int priority; /* The priority */
};
static struct ipr_data ipr_data[NR_IRQS];
static void enable_ipr_irq(unsigned int irq);
static void disable_ipr_irq(unsigned int irq);
/* shutdown is same as "disable" */
#define shutdown_ipr_irq disable_ipr_irq
static void mask_and_ack_ipr(unsigned int);
static void end_ipr_irq(unsigned int irq);
static unsigned int startup_ipr_irq(unsigned int irq)
{
enable_ipr_irq(irq);
return 0; /* never anything pending */
}
static struct hw_interrupt_type ipr_irq_type = {
.typename = "IPR-IRQ",
.startup = startup_ipr_irq,
.shutdown = shutdown_ipr_irq,
.enable = enable_ipr_irq,
.disable = disable_ipr_irq,
.ack = mask_and_ack_ipr,
.end = end_ipr_irq
};
static void disable_ipr_irq(unsigned int irq)
{
unsigned long val;
unsigned int addr = ipr_data[irq].addr;
unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
struct ipr_data *p = get_irq_chip_data(irq);
/* Set the priority in IPR to 0 */
val = ctrl_inw(addr);
val &= mask;
ctrl_outw(val, addr);
ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
}
static void enable_ipr_irq(unsigned int irq)
{
unsigned long val;
unsigned int addr = ipr_data[irq].addr;
int priority = ipr_data[irq].priority;
unsigned short value = (priority << ipr_data[irq].shift);
struct ipr_data *p = get_irq_chip_data(irq);
/* Set priority in IPR back to original value */
val = ctrl_inw(addr);
val |= value;
ctrl_outw(val, addr);
ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
}
static void mask_and_ack_ipr(unsigned int irq)
{
disable_ipr_irq(irq);
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
/* This is needed when we use edge triggered setting */
/* XXX: Is it really needed? */
if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
/* Clear external interrupt request */
int a = ctrl_inb(INTC_IRR0);
a &= ~(1 << (irq - IRQ0_IRQ));
ctrl_outb(a, INTC_IRR0);
}
#endif
}
static void end_ipr_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_ipr_irq(irq);
}
static struct irq_chip ipr_irq_chip = {
.name = "ipr",
.mask = disable_ipr_irq,
.unmask = enable_ipr_irq,
.mask_ack = disable_ipr_irq,
};
void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
{
struct ipr_data ipr_data;
disable_irq_nosync(irq);
ipr_data[irq].addr = addr;
ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
ipr_data[irq].priority = priority;
irq_desc[irq].chip = &ipr_irq_type;
disable_ipr_irq(irq);
ipr_data.addr = addr;
ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */
ipr_data.priority = priority;
set_irq_chip_and_handler(irq, &ipr_irq_chip, handle_level_irq);
set_irq_chip_data(irq, &ipr_data);
enable_ipr_irq(irq);
}
/* XXX: This needs to die a horrible death.. */
void __init init_IRQ(void)
{
#ifndef CONFIG_CPU_SUBTYPE_SH7780
......
arch/sh/kernel/cpu/sh3/ex.S
View file @ 9eb20074
......@@ -49,198 +49,3 @@ ENTRY(nmi_slot)
#endif
ENTRY(user_break_point_trap)
.long break_point_trap /* 1E0 */
ENTRY(interrupt_table)
! external hardware
.long do_IRQ ! 0000 /* 200 */
.long do_IRQ ! 0001
.long do_IRQ ! 0010
.long do_IRQ ! 0011
.long do_IRQ ! 0100
.long do_IRQ ! 0101
.long do_IRQ ! 0110
.long do_IRQ ! 0111
.long do_IRQ ! 1000 /* 300 */
.long do_IRQ ! 1001
.long do_IRQ ! 1010
.long do_IRQ ! 1011
.long do_IRQ ! 1100
.long do_IRQ ! 1101
.long do_IRQ ! 1110
.long exception_error
! Internal hardware
.long do_IRQ ! TMU0 tuni0 /* 400 */
.long do_IRQ ! TMU1 tuni1
.long do_IRQ ! TMU2 tuni2
.long do_IRQ ! ticpi2
.long do_IRQ ! RTC ati
.long do_IRQ ! pri
.long do_IRQ ! cui
.long do_IRQ ! SCI eri
.long do_IRQ ! rxi /* 500 */
.long do_IRQ ! txi
.long do_IRQ ! tei
.long do_IRQ ! WDT iti /* 560 */
.long do_IRQ ! REF rcmi
.long do_IRQ ! rovi
.long do_IRQ
.long do_IRQ /* 5E0 */
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7300) || \
defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7710)
.long do_IRQ ! 32 IRQ irq0 /* 600 */
.long do_IRQ ! 33 irq1
.long do_IRQ ! 34 irq2
.long do_IRQ ! 35 irq3
.long do_IRQ ! 36 irq4
.long do_IRQ ! 37 irq5
.long do_IRQ ! 38
.long do_IRQ ! 39
.long do_IRQ ! 40 PINT pint0-7 /* 700 */
.long do_IRQ ! 41 pint8-15
.long do_IRQ ! 42
.long do_IRQ ! 43
.long do_IRQ ! 44
.long do_IRQ ! 45
.long do_IRQ ! 46
.long do_IRQ ! 47
.long do_IRQ ! 48 DMAC dei0 /* 800 */
.long do_IRQ ! 49 dei1
.long do_IRQ ! 50 dei2
.long do_IRQ ! 51 dei3
.long do_IRQ ! 52 IrDA eri1
.long do_IRQ ! 53 rxi1
.long do_IRQ ! 54 bri1
.long do_IRQ ! 55 txi1
.long do_IRQ ! 56 SCIF eri2
.long do_IRQ ! 57 rxi2
.long do_IRQ ! 58 bri2
.long do_IRQ ! 59 txi2
.long do_IRQ ! 60 ADC adi /* 980 */
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
.long exception_none ! 61 /* 9A0 */
.long exception_none ! 62
.long exception_none ! 63
.long exception_none ! 64 /* A00 */
.long do_IRQ ! 65 USB usi0
.long do_IRQ ! 66 usi1
.long exception_none ! 67
.long exception_none ! 68
.long exception_none ! 69
.long exception_none ! 70
.long exception_none ! 71
.long exception_none ! 72 /* B00 */
.long exception_none ! 73
.long exception_none ! 74
.long exception_none ! 75
.long exception_none ! 76
.long exception_none ! 77
.long exception_none ! 78
.long exception_none ! 79
.long do_IRQ ! 80 TPU0 tpi0 /* C00 */
.long do_IRQ ! 81 TPU1 tpi1
.long exception_none ! 82
.long exception_none ! 83
.long do_IRQ ! 84 TPU2 tpi2
.long do_IRQ ! 85 TPU3 tpi3 /* CA0 */
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7300)
.long do_IRQ ! 61 LCDC lcdi /* 9A0 */
.long do_IRQ ! 62 PCC pcc0i
.long do_IRQ ! 63 pcc1i /* 9E0 */
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
.long exception_none ! 61 /* 9A0 */
.long exception_none ! 62
.long exception_none ! 63
.long exception_none ! 64 /* A00 */
.long exception_none ! 65
.long exception_none ! 66
.long exception_none ! 67
.long exception_none ! 68
.long exception_none ! 69
.long exception_none ! 70
.long exception_none ! 71
.long exception_none ! 72 /* B00 */
.long exception_none ! 73
.long exception_none ! 74
.long exception_none ! 75
.long do_IRQ ! 76 DMAC2 dei4 /* B80 */
.long do_IRQ ! 77 DMAC2 dei5
.long exception_none ! 78
.long do_IRQ ! 79 IPSEC ipseci /* BE0 */
.long do_IRQ ! 80 EDMAC eint0 /* C00 */
.long do_IRQ ! 81 EDMAC eint1
.long do_IRQ ! 82 EDMAC eint2
.long exception_none ! 83 /* C60 */
.long exception_none ! 84
.long exception_none ! 85
.long exception_none ! 86
.long exception_none ! 87
.long exception_none ! 88 /* D00 */
.long exception_none ! 89
.long exception_none ! 90
.long exception_none ! 91
.long exception_none ! 92
.long exception_none ! 93
.long exception_none ! 94
.long exception_none ! 95
.long do_IRQ ! 96 SIOF eri0 /* E00 */
.long do_IRQ ! 97 txi0
.long do_IRQ ! 98 rxi0
.long do_IRQ ! 99 cci0
.long do_IRQ ! 100 eri1 /* E80 */
.long do_IRQ ! 101 txi1
.long do_IRQ ! 102 rxi2
.long do_IRQ ! 103 cci3
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
.long do_IRQ ! 64
.long do_IRQ ! 65
.long do_IRQ ! 66
.long do_IRQ ! 67
.long do_IRQ ! 68
.long do_IRQ ! 69
.long do_IRQ ! 70
.long do_IRQ ! 71
.long do_IRQ ! 72
.long do_IRQ ! 73
.long do_IRQ ! 74
.long do_IRQ ! 75
.long do_IRQ ! 76
.long do_IRQ ! 77
.long do_IRQ ! 78
.long do_IRQ ! 79
.long do_IRQ ! 80 SCIF0(SH7300)
.long do_IRQ ! 81
.long do_IRQ ! 82
.long do_IRQ ! 83
.long do_IRQ ! 84
.long do_IRQ ! 85
.long do_IRQ ! 86
.long do_IRQ ! 87
.long do_IRQ ! 88
.long do_IRQ ! 89
.long do_IRQ ! 90
.long do_IRQ ! 91
.long do_IRQ ! 92
.long do_IRQ ! 93
.long do_IRQ ! 94
.long do_IRQ ! 95
.long do_IRQ ! 96
.long do_IRQ ! 97
.long do_IRQ ! 98
.long do_IRQ ! 99
.long do_IRQ ! 100
.long do_IRQ ! 101
.long do_IRQ ! 102
.long do_IRQ ! 103
.long do_IRQ ! 104
.long do_IRQ ! 105
.long do_IRQ ! 106
.long do_IRQ ! 107
.long do_IRQ ! 108
#endif
#endif
arch/sh/kernel/cpu/sh4/ex.S
View file @ 9eb20074
This diff is collapsed.
arch/sh/kernel/entry.S
View file @ 9eb20074
/* $Id: entry.S,v 1.37 2004/06/11 13:02:46 doyu Exp $
*
/*
* linux/arch/sh/entry.S
*
* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
* Copyright (C) 2003 - 2006 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
......@@ -78,7 +77,6 @@ OFF_TRA = (16*4+6*4)
#define k3 r3
#define k4 r4
#define k_ex_code r2_bank /* r2_bank1 */
#define g_imask r6 /* r6_bank1 */
#define k_g_imask r6_bank /* r6_bank1 */
#define current r7 /* r7_bank1 */
......@@ -691,7 +689,7 @@ interrupt:
0:
#endif /* defined(CONFIG_KGDB_NMI) */
bra handle_exception
mov.l @k2, k2
mov #-1, k2 ! interrupt exception marker
.align 2
1: .long EXPEVT
......@@ -717,8 +715,7 @@ ENTRY(handle_exception)
add current, k1
mov k1, r15 ! change to kernel stack
!
1: mov #-1, k4
mov.l 2f, k1
1: mov.l 2f, k1
!
#ifdef CONFIG_SH_DSP
mov.l r2, @-r15 ! Save r2, we need another reg
......@@ -763,6 +760,8 @@ skip_save:
#endif
! Save the user registers on the stack.
mov.l k2, @-r15 ! EXPEVT
mov #-1, k4
mov.l k4, @-r15 ! set TRA (default: -1)
!
sts.l macl, @-r15
......@@ -797,8 +796,21 @@ skip_save:
mov.l r2, @-r15
mov.l r1, @-r15
mov.l r0, @-r15
! Then, dispatch to the handler, according to the exception code.
stc k_ex_code, r8
/*
* This gets a bit tricky.. in the INTEVT case we don't want to use
* the VBR offset as a destination in the jump call table, since all
* of the destinations are the same. In this case, (interrupt) sets
* a marker in r2 (now r2_bank since SR.RB changed), which we check
* to determine the exception type. For all other exceptions, we
* forcibly read EXPEVT from memory and fix up the jump address, in
* the interrupt exception case we jump to do_IRQ() and defer the
* INTEVT read until there. As a bonus, we can also clean up the SR.RB
* checks that do_IRQ() was doing..
*/
stc r2_bank, r8
cmp/pz r8
bf interrupt_exception
shlr2 r8
shlr r8
mov.l 4f, r9
......@@ -806,6 +818,8 @@ skip_save:
mov.l @r9, r9
jmp @r9
nop
rts
nop
.align 2
1: .long 0x00001000 ! DSP=1
......@@ -813,8 +827,17 @@ skip_save:
3: .long 0xcfffffff ! RB=0, BL=0
4: .long exception_handling_table
interrupt_exception:
mov.l 1f, r9
jmp @r9
nop
rts
nop
.align 2
1: .long do_IRQ
.align 2
ENTRY(exception_none)
rts
nop
arch/sh/kernel/irq.c
View file @ 9eb20074
......@@ -11,12 +11,15 @@
#include <linux/module.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
#include <asm/thread_info.h>
#include <asm/cpu/mmu_context.h>
atomic_t irq_err_count;
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
* each architecture has to answer this themselves, it doesn't deserve
......@@ -24,6 +27,7 @@
*/
void ack_bad_irq(unsigned int irq)
{
atomic_inc(&irq_err_count);
printk("unexpected IRQ trap at vector %02x\n", irq);
}
......@@ -47,8 +51,10 @@ int show_interrupts(struct seq_file *p, void *v)
if (!action)
goto unlock;
seq_printf(p, "%3d: ",i);
seq_printf(p, "%10u ", kstat_irqs(i));
seq_printf(p, " %14s", irq_desc[i].chip->typename);
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
seq_printf(p, " %14s", irq_desc[i].chip->name);
seq_printf(p, "-%s", handle_irq_name(irq_desc[i].handle_irq));
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
......@@ -56,7 +62,9 @@ int show_interrupts(struct seq_file *p, void *v)
seq_putc(p, '\n');
unlock:
spin_unlock_irqrestore(&irq_desc[i].lock, flags);
}
} else if (i == NR_IRQS)
seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
return 0;
}
#endif
......@@ -78,7 +86,8 @@ asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7,
struct pt_regs regs)
{
int irq = r4;
struct pt_regs *old_regs = set_irq_regs(&regs);
int irq;
#ifdef CONFIG_4KSTACKS
union irq_ctx *curctx, *irqctx;
#endif
......@@ -102,20 +111,9 @@ asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
#endif
#ifdef CONFIG_CPU_HAS_INTEVT
__asm__ __volatile__ (
#ifdef CONFIG_CPU_HAS_SR_RB
"stc r2_bank, %0\n\t"
irq = (ctrl_inl(INTEVT) >> 5) - 16;
#else
"mov.l @%1, %0\n\t"
#endif
"shlr2 %0\n\t"
"shlr2 %0\n\t"
"shlr %0\n\t"
"add #-16, %0\n\t"
: "=z" (irq), "=r" (r4)
: "1" (INTEVT)
: "memory"
);
irq = r4;
#endif
irq = irq_demux(irq);
......@@ -139,25 +137,25 @@ asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
__asm__ __volatile__ (
"mov %0, r4 \n"
"mov %1, r5 \n"
"mov r15, r9 \n"
"jsr @%2 \n"
"jsr @%1 \n"
/* swith to the irq stack */
" mov %3, r15 \n"
" mov %2, r15 \n"
/* restore the stack (ring zero) */
"mov r9, r15 \n"
: /* no outputs */
: "r" (irq), "r" (&regs), "r" (__do_IRQ), "r" (isp)
: "r" (irq), "r" (generic_handle_irq), "r" (isp)
/* XXX: A somewhat excessive clobber list? -PFM */
: "memory", "r0", "r1", "r2", "r3", "r4",
"r5", "r6", "r7", "r8", "t", "pr"
);
} else
#endif
__do_IRQ(irq, &regs);
generic_handle_irq(irq);
irq_exit();
set_irq_regs(old_regs);
return 1;
}
......
arch/sh/kernel/process.c
View file @ 9eb20074
......@@ -5,6 +5,7 @@
* Copyright (C) 1995 Linus Torvalds
*
* SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
* Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
*/
/*
......@@ -290,6 +291,24 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
static void
ubc_set_tracing(int asid, unsigned long pc)
{
#if defined(CONFIG_CPU_SH4A)
unsigned long val;
val = (UBC_CBR_ID_INST | UBC_CBR_RW_READ | UBC_CBR_CE);
val |= (UBC_CBR_AIE | UBC_CBR_AIV_SET(asid));
ctrl_outl(val, UBC_CBR0);
ctrl_outl(pc, UBC_CAR0);
ctrl_outl(0x0, UBC_CAMR0);
ctrl_outl(0x0, UBC_CBCR);
val = (UBC_CRR_RES | UBC_CRR_PCB | UBC_CRR_BIE);
ctrl_outl(val, UBC_CRR0);
/* Read UBC register that we writed last. For chekking UBC Register changed */
val = ctrl_inl(UBC_CRR0);
#else /* CONFIG_CPU_SH4A */
ctrl_outl(pc, UBC_BARA);
#ifdef CONFIG_MMU
......@@ -307,6 +326,7 @@ ubc_set_tracing(int asid, unsigned long pc)
ctrl_outw(BBR_INST | BBR_READ, UBC_BBRA);
ctrl_outw(BRCR_PCBA, UBC_BRCR);
}
#endif /* CONFIG_CPU_SH4A */
}
/*
......@@ -359,8 +379,13 @@ struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *ne
#endif
ubc_set_tracing(asid, next->thread.ubc_pc);
} else {
#if defined(CONFIG_CPU_SH4A)
ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
#else
ctrl_outw(0, UBC_BBRA);
ctrl_outw(0, UBC_BBRB);
#endif
}
return prev;
......@@ -460,8 +485,13 @@ asmlinkage void break_point_trap(unsigned long r4, unsigned long r5,
struct pt_regs regs)
{
/* Clear tracing. */
#if defined(CONFIG_CPU_SH4A)
ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
#else
ctrl_outw(0, UBC_BBRA);
ctrl_outw(0, UBC_BBRB);
#endif
current->thread.ubc_pc = 0;
ubc_usercnt -= 1;
......
arch/sh/kernel/time.c
View file @ 9eb20074
......@@ -47,6 +47,7 @@ unsigned long long __attribute__ ((weak)) sched_clock(void)
return (unsigned long long)jiffies * (1000000000 / HZ);
}
#ifndef CONFIG_GENERIC_TIME
void do_gettimeofday(struct timeval *tv)
{
unsigned long seq;
......@@ -99,6 +100,7 @@ int do_settimeofday(struct timespec *tv)
return 0;
}
EXPORT_SYMBOL(do_settimeofday);
#endif /* !CONFIG_GENERIC_TIME */
/* last time the RTC clock got updated */
static long last_rtc_update;
......@@ -107,13 +109,14 @@ static long last_rtc_update;
* handle_timer_tick() needs to keep up the real-time clock,
* as well as call the "do_timer()" routine every clocktick
*/
void handle_timer_tick(struct pt_regs *regs)
void handle_timer_tick(void)
{
do_timer(1);
#ifndef CONFIG_SMP
update_process_times(user_mode(regs));
update_process_times(user_mode(get_irq_regs()));
#endif
profile_tick(CPU_PROFILING, regs);
if (current->pid)
profile_tick(CPU_PROFILING);
#ifdef CONFIG_HEARTBEAT
if (sh_mv.mv_heartbeat != NULL)
......
arch/sh/kernel/timers/timer-tmu.c
View file @ 9eb20074
......@@ -80,8 +80,7 @@ static unsigned long tmu_timer_get_offset(void)
return count;
}
static irqreturn_t tmu_timer_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
{
unsigned long timer_status;
......@@ -98,7 +97,7 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dev_id,
* locally disabled. -arca
*/
write_seqlock(&xtime_lock);
handle_timer_tick(regs);
handle_timer_tick();
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
......@@ -111,60 +110,6 @@ static struct irqaction tmu_irq = {
.mask = CPU_MASK_NONE,
};
/*
* Hah! We'll see if this works (switching from usecs to nsecs).
*/
static unsigned long tmu_timer_get_frequency(void)
{
u32 freq;
struct timespec ts1, ts2;
unsigned long diff_nsec;
unsigned long factor;
/* Setup the timer: We don't want to generate interrupts, just
* have it count down at its natural rate.
*/
ctrl_outb(0, TMU_TSTR);
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
#endif
ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
ctrl_outl(0xffffffff, TMU0_TCOR);
ctrl_outl(0xffffffff, TMU0_TCNT);
rtc_sh_get_time(&ts2);
do {
rtc_sh_get_time(&ts1);
} while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
/* actually start the timer */
ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
do {
rtc_sh_get_time(&ts2);
} while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
if (ts2.tv_nsec < ts1.tv_nsec) {
ts2.tv_nsec += 1000000000;
ts2.tv_sec--;
}
diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
/* this should work well if the RTC has a precision of n Hz, where
* n is an integer. I don't think we have to worry about the other
* cases. */
factor = (1000000000 + diff_nsec/2) / diff_nsec;
if (factor * diff_nsec > 1100000000 ||
factor * diff_nsec < 900000000)
panic("weird RTC (diff_nsec %ld)", diff_nsec);
return freq * factor;
}
static void tmu_clk_init(struct clk *clk)
{
u8 divisor = TMU0_TCR_INIT & 0x7;
......@@ -232,12 +177,12 @@ struct sys_timer_ops tmu_timer_ops = {
.init = tmu_timer_init,
.start = tmu_timer_start,
.stop = tmu_timer_stop,
.get_frequency = tmu_timer_get_frequency,
#ifndef CONFIG_GENERIC_TIME
.get_offset = tmu_timer_get_offset,
#endif
};
struct sys_timer tmu_timer = {
.name = "tmu",
.ops = &tmu_timer_ops,
};
arch/sh/mm/consistent.c
View file @ 9eb20074
......@@ -28,6 +28,7 @@ void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *handle)
split_page(page, order);
ret = page_address(page);
memset(ret, 0, size);
*handle = virt_to_phys(ret);
/*
......
drivers/rtc/rtc-sh.c
View file @ 9eb20074
......@@ -160,7 +160,7 @@ static int sh_rtc_open(struct device *dev)
tmp |= RCR1_CIE;
writeb(tmp, rtc->regbase + RCR1);
ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, SA_INTERRUPT,
ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, IRQF_DISABLED,
"sh-rtc period", dev);
if (unlikely(ret)) {
dev_err(dev, "request period IRQ failed with %d, IRQ %d\n",
......@@ -168,7 +168,7 @@ static int sh_rtc_open(struct device *dev)
return ret;
}
ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, SA_INTERRUPT,
ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED,
"sh-rtc carry", dev);
if (unlikely(ret)) {
dev_err(dev, "request carry IRQ failed with %d, IRQ %d\n",
......@@ -177,7 +177,7 @@ static int sh_rtc_open(struct device *dev)
goto err_bad_carry;
}
ret = request_irq(rtc->alarm_irq, sh_rtc_interrupt, SA_INTERRUPT,
ret = request_irq(rtc->alarm_irq, sh_rtc_interrupt, IRQF_DISABLED,
"sh-rtc alarm", dev);
if (unlikely(ret)) {
dev_err(dev, "request alarm IRQ failed with %d, IRQ %d\n",
......
drivers/serial/sh-sci.c
View file @ 9eb20074
......@@ -808,7 +808,7 @@ static int sci_request_irq(struct sci_port *port)
}
if (request_irq(port->irqs[0], sci_mpxed_interrupt,
SA_INTERRUPT, "sci", port)) {
IRQF_DISABLED, "sci", port)) {
printk(KERN_ERR "sci: Cannot allocate irq.\n");
return -ENODEV;
}
......@@ -817,7 +817,7 @@ static int sci_request_irq(struct sci_port *port)
if (!port->irqs[i])
continue;
if (request_irq(port->irqs[i], handlers[i],
SA_INTERRUPT, desc[i], port)) {
IRQF_DISABLED, desc[i], port)) {
printk(KERN_ERR "sci: Cannot allocate irq.\n");
return -ENODEV;
}
......
include/asm-sh/cpu-sh4/ubc.h
View file @ 9eb20074
......@@ -3,6 +3,7 @@
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
* Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
......@@ -11,6 +12,41 @@
#ifndef __ASM_CPU_SH4_UBC_H
#define __ASM_CPU_SH4_UBC_H
#if defined(CONFIG_CPU_SH4A)
#define UBC_CBR0 0xff200000
#define UBC_CRR0 0xff200004
#define UBC_CAR0 0xff200008
#define UBC_CAMR0 0xff20000c
#define UBC_CBR1 0xff200020
#define UBC_CRR1 0xff200024
#define UBC_CAR1 0xff200028
#define UBC_CAMR1 0xff20002c
#define UBC_CDR1 0xff200030
#define UBC_CDMR1 0xff200034
#define UBC_CETR1 0xff200038
#define UBC_CCMFR 0xff200600
#define UBC_CBCR 0xff200620
/* CBR */
#define UBC_CBR_AIE (0x01<<30)
#define UBC_CBR_ID_INST (0x01<<4)
#define UBC_CBR_RW_READ (0x01<<1)
#define UBC_CBR_CE (0x01)
#define UBC_CBR_AIV_MASK (0x00FF0000)
#define UBC_CBR_AIV_SHIFT (16)
#define UBC_CBR_AIV_SET(asid) (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
#define UBC_CBR_INIT 0x20000000
/* CRR */
#define UBC_CRR_RES (0x01<<13)
#define UBC_CRR_PCB (0x01<<1)
#define UBC_CRR_BIE (0x01)
#define UBC_CRR_INIT 0x00002000
#else /* CONFIG_CPU_SH4 */
#define UBC_BARA 0xff200000
#define UBC_BAMRA 0xff200004
#define UBC_BBRA 0xff200008
......@@ -22,6 +58,7 @@
#define UBC_BDRB 0xff200018
#define UBC_BDMRB 0xff20001c
#define UBC_BRCR 0xff200020
#endif /* CONFIG_CPU_SH4 */
#endif /* __ASM_CPU_SH4_UBC_H */
include/asm-sh/hw_irq.h
View file @ 9eb20074
#ifndef __ASM_SH_HW_IRQ_H
#define __ASM_SH_HW_IRQ_H
#include <asm/atomic.h>
extern atomic_t irq_err_count;
#endif /* __ASM_SH_HW_IRQ_H */
include/asm-sh/irq.h
View file @ 9eb20074
......@@ -697,13 +697,15 @@ extern int ipr_irq_demux(int irq);
#define INTC2_INTPRI_OFFSET 0x00
void make_intc2_irq(unsigned int irq,
unsigned int ipr_offset, unsigned int ipr_shift,
unsigned int msk_offset, unsigned int msk_shift,
unsigned int priority);
struct intc2_data {
unsigned short irq;
unsigned char ipr_offset, ipr_shift;
unsigned char msk_offset, msk_shift;
unsigned char priority;
};
void make_intc2_irq(struct intc2_data *);
void init_IRQ_intc2(void);
void intc2_add_clear_irq(int irq, int (*fn)(int));
#endif
extern int shmse_irq_demux(int irq);
......
include/asm-sh/irq_regs.h 0 → 100644
View file @ 9eb20074
#include <asm-generic/irq_regs.h>
include/asm-sh/timer.h
View file @ 9eb20074
......@@ -8,8 +8,9 @@ struct sys_timer_ops {
int (*init)(void);
int (*start)(void);
int (*stop)(void);
#ifndef CONFIG_GENERIC_TIME
unsigned long (*get_offset)(void);
unsigned long (*get_frequency)(void);
#endif
};
struct sys_timer {
......@@ -24,21 +25,17 @@ struct sys_timer {
extern struct sys_timer tmu_timer;
extern struct sys_timer *sys_timer;
#ifndef CONFIG_GENERIC_TIME
static inline unsigned long get_timer_offset(void)
{
return sys_timer->ops->get_offset();
}
static inline unsigned long get_timer_frequency(void)
{
return sys_timer->ops->get_frequency();
}
#endif
/* arch/sh/kernel/timers/timer.c */
struct sys_timer *get_sys_timer(void);
/* arch/sh/kernel/time.c */
void handle_timer_tick(struct pt_regs *);
void handle_timer_tick(void);
#endif /* __ASM_SH_TIMER_H */
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