Commit 9f73e112 authored by Michael Grzeschik's avatar Michael Grzeschik Committed by David S. Miller

net: dsa: microchip: ksz8795: move register offsets and shifts to separate struct

In order to get this driver used with other switches the functions need
to use different offsets and register shifts. This patch changes the
direct use of the register defines to register description structures,
which can be set depending on the chips register layout.
Signed-off-by: default avatarMichael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c2ac4d2a
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Microchip KSZ8XXX series register access
*
* Copyright (C) 2020 Pengutronix, Michael Grzeschik <kernel@pengutronix.de>
*/
#ifndef __KSZ8XXX_H
#define __KSZ8XXX_H
#include <linux/kernel.h>
enum ksz_regs {
REG_IND_CTRL_0,
REG_IND_DATA_8,
REG_IND_DATA_CHECK,
REG_IND_DATA_HI,
REG_IND_DATA_LO,
REG_IND_MIB_CHECK,
P_FORCE_CTRL,
P_LINK_STATUS,
P_LOCAL_CTRL,
P_NEG_RESTART_CTRL,
P_REMOTE_STATUS,
P_SPEED_STATUS,
S_TAIL_TAG_CTRL,
};
enum ksz_masks {
PORT_802_1P_REMAPPING,
SW_TAIL_TAG_ENABLE,
MIB_COUNTER_OVERFLOW,
MIB_COUNTER_VALID,
VLAN_TABLE_FID,
VLAN_TABLE_MEMBERSHIP,
VLAN_TABLE_VALID,
STATIC_MAC_TABLE_VALID,
STATIC_MAC_TABLE_USE_FID,
STATIC_MAC_TABLE_FID,
STATIC_MAC_TABLE_OVERRIDE,
STATIC_MAC_TABLE_FWD_PORTS,
DYNAMIC_MAC_TABLE_ENTRIES_H,
DYNAMIC_MAC_TABLE_MAC_EMPTY,
DYNAMIC_MAC_TABLE_NOT_READY,
DYNAMIC_MAC_TABLE_ENTRIES,
DYNAMIC_MAC_TABLE_FID,
DYNAMIC_MAC_TABLE_SRC_PORT,
DYNAMIC_MAC_TABLE_TIMESTAMP,
};
enum ksz_shifts {
VLAN_TABLE_MEMBERSHIP_S,
VLAN_TABLE,
STATIC_MAC_FWD_PORTS,
STATIC_MAC_FID,
DYNAMIC_MAC_ENTRIES_H,
DYNAMIC_MAC_ENTRIES,
DYNAMIC_MAC_FID,
DYNAMIC_MAC_TIMESTAMP,
DYNAMIC_MAC_SRC_PORT,
};
struct ksz8 {
const u8 *regs;
const u32 *masks;
const u8 *shifts;
void *priv;
};
#endif
This diff is collapsed.
...@@ -98,7 +98,6 @@ ...@@ -98,7 +98,6 @@
#define REG_SW_CTRL_10 0x0C #define REG_SW_CTRL_10 0x0C
#define SW_TAIL_TAG_ENABLE BIT(1)
#define SW_PASS_PAUSE BIT(0) #define SW_PASS_PAUSE BIT(0)
#define REG_SW_CTRL_11 0x0D #define REG_SW_CTRL_11 0x0D
...@@ -150,7 +149,6 @@ ...@@ -150,7 +149,6 @@
#define REG_PORT_4_CTRL_2 0x42 #define REG_PORT_4_CTRL_2 0x42
#define REG_PORT_5_CTRL_2 0x52 #define REG_PORT_5_CTRL_2 0x52
#define PORT_802_1P_REMAPPING BIT(7)
#define PORT_INGRESS_FILTER BIT(6) #define PORT_INGRESS_FILTER BIT(6)
#define PORT_DISCARD_NON_VID BIT(5) #define PORT_DISCARD_NON_VID BIT(5)
#define PORT_FORCE_FLOW_CTRL BIT(4) #define PORT_FORCE_FLOW_CTRL BIT(4)
...@@ -319,14 +317,12 @@ ...@@ -319,14 +317,12 @@
#define REG_PORT_CTRL_5 0x05 #define REG_PORT_CTRL_5 0x05
#define REG_PORT_CTRL_7 0x07
#define REG_PORT_STATUS_0 0x08 #define REG_PORT_STATUS_0 0x08
#define REG_PORT_STATUS_1 0x09 #define REG_PORT_STATUS_1 0x09
#define REG_PORT_LINK_MD_CTRL 0x0A #define REG_PORT_LINK_MD_CTRL 0x0A
#define REG_PORT_LINK_MD_RESULT 0x0B #define REG_PORT_LINK_MD_RESULT 0x0B
#define REG_PORT_CTRL_9 0x0C #define REG_PORT_CTRL_9 0x0C
#define REG_PORT_CTRL_10 0x0D #define REG_PORT_CTRL_10 0x0D
#define REG_PORT_STATUS_2 0x0E
#define REG_PORT_STATUS_3 0x0F #define REG_PORT_STATUS_3 0x0F
#define REG_PORT_CTRL_12 0xA0 #define REG_PORT_CTRL_12 0xA0
...@@ -356,8 +352,6 @@ ...@@ -356,8 +352,6 @@
#define REG_SW_MAC_ADDR_4 0x6C #define REG_SW_MAC_ADDR_4 0x6C
#define REG_SW_MAC_ADDR_5 0x6D #define REG_SW_MAC_ADDR_5 0x6D
#define REG_IND_CTRL_0 0x6E
#define TABLE_EXT_SELECT_S 5 #define TABLE_EXT_SELECT_S 5
#define TABLE_EEE_V 1 #define TABLE_EEE_V 1
#define TABLE_ACL_V 2 #define TABLE_ACL_V 2
...@@ -383,23 +377,13 @@ ...@@ -383,23 +377,13 @@
#define TABLE_ENTRY_MASK 0x03FF #define TABLE_ENTRY_MASK 0x03FF
#define TABLE_EXT_ENTRY_MASK 0x0FFF #define TABLE_EXT_ENTRY_MASK 0x0FFF
#define REG_IND_DATA_8 0x70
#define REG_IND_DATA_7 0x71
#define REG_IND_DATA_6 0x72
#define REG_IND_DATA_5 0x73 #define REG_IND_DATA_5 0x73
#define REG_IND_DATA_4 0x74
#define REG_IND_DATA_3 0x75
#define REG_IND_DATA_2 0x76 #define REG_IND_DATA_2 0x76
#define REG_IND_DATA_1 0x77 #define REG_IND_DATA_1 0x77
#define REG_IND_DATA_0 0x78 #define REG_IND_DATA_0 0x78
#define REG_IND_DATA_PME_EEE_ACL 0xA0 #define REG_IND_DATA_PME_EEE_ACL 0xA0
#define REG_IND_DATA_CHECK REG_IND_DATA_6
#define REG_IND_MIB_CHECK REG_IND_DATA_4
#define REG_IND_DATA_HI REG_IND_DATA_7
#define REG_IND_DATA_LO REG_IND_DATA_3
#define REG_INT_STATUS 0x7C #define REG_INT_STATUS 0x7C
#define REG_INT_ENABLE 0x7D #define REG_INT_ENABLE 0x7D
...@@ -856,12 +840,6 @@ ...@@ -856,12 +840,6 @@
#define P_MIRROR_CTRL REG_PORT_CTRL_1 #define P_MIRROR_CTRL REG_PORT_CTRL_1
#define P_802_1P_CTRL REG_PORT_CTRL_2 #define P_802_1P_CTRL REG_PORT_CTRL_2
#define P_STP_CTRL REG_PORT_CTRL_2 #define P_STP_CTRL REG_PORT_CTRL_2
#define P_LOCAL_CTRL REG_PORT_CTRL_7
#define P_REMOTE_STATUS REG_PORT_STATUS_0
#define P_FORCE_CTRL REG_PORT_CTRL_9
#define P_NEG_RESTART_CTRL REG_PORT_CTRL_10
#define P_SPEED_STATUS REG_PORT_STATUS_1
#define P_LINK_STATUS REG_PORT_STATUS_2
#define P_PASS_ALL_CTRL REG_PORT_CTRL_12 #define P_PASS_ALL_CTRL REG_PORT_CTRL_12
#define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12 #define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12
#define P_DROP_TAG_CTRL REG_PORT_CTRL_13 #define P_DROP_TAG_CTRL REG_PORT_CTRL_13
...@@ -876,7 +854,6 @@ ...@@ -876,7 +854,6 @@
#define S_MIRROR_CTRL REG_SW_CTRL_3 #define S_MIRROR_CTRL REG_SW_CTRL_3
#define S_REPLACE_VID_CTRL REG_SW_CTRL_4 #define S_REPLACE_VID_CTRL REG_SW_CTRL_4
#define S_PASS_PAUSE_CTRL REG_SW_CTRL_10 #define S_PASS_PAUSE_CTRL REG_SW_CTRL_10
#define S_TAIL_TAG_CTRL REG_SW_CTRL_10
#define S_802_1P_PRIO_CTRL REG_SW_CTRL_12 #define S_802_1P_PRIO_CTRL REG_SW_CTRL_12
#define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0 #define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0
#define S_IPV6_MLD_CTRL REG_SW_CTRL_21 #define S_IPV6_MLD_CTRL REG_SW_CTRL_21
...@@ -889,65 +866,6 @@ ...@@ -889,65 +866,6 @@
/* 148,800 frames * 67 ms / 100 */ /* 148,800 frames * 67 ms / 100 */
#define BROADCAST_STORM_VALUE 9969 #define BROADCAST_STORM_VALUE 9969
/**
* STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
* STATIC_MAC_TABLE_FWD_PORTS 00-001F0000-00000000
* STATIC_MAC_TABLE_VALID 00-00200000-00000000
* STATIC_MAC_TABLE_OVERRIDE 00-00400000-00000000
* STATIC_MAC_TABLE_USE_FID 00-00800000-00000000
* STATIC_MAC_TABLE_FID 00-7F000000-00000000
*/
#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
#define STATIC_MAC_TABLE_FWD_PORTS 0x001F0000
#define STATIC_MAC_TABLE_VALID 0x00200000
#define STATIC_MAC_TABLE_OVERRIDE 0x00400000
#define STATIC_MAC_TABLE_USE_FID 0x00800000
#define STATIC_MAC_TABLE_FID 0x7F000000
#define STATIC_MAC_FWD_PORTS_S 16
#define STATIC_MAC_FID_S 24
/**
* VLAN_TABLE_FID 00-007F007F-007F007F
* VLAN_TABLE_MEMBERSHIP 00-0F800F80-0F800F80
* VLAN_TABLE_VALID 00-10001000-10001000
*/
#define VLAN_TABLE_FID 0x007F
#define VLAN_TABLE_MEMBERSHIP 0x0F80
#define VLAN_TABLE_VALID 0x1000
#define VLAN_TABLE_MEMBERSHIP_S 7
#define VLAN_TABLE_S 16
/**
* DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
* DYNAMIC_MAC_TABLE_FID 00-007F0000-00000000
* DYNAMIC_MAC_TABLE_NOT_READY 00-00800000-00000000
* DYNAMIC_MAC_TABLE_SRC_PORT 00-07000000-00000000
* DYNAMIC_MAC_TABLE_TIMESTAMP 00-18000000-00000000
* DYNAMIC_MAC_TABLE_ENTRIES 7F-E0000000-00000000
* DYNAMIC_MAC_TABLE_MAC_EMPTY 80-00000000-00000000
*/
#define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
#define DYNAMIC_MAC_TABLE_FID 0x007F0000
#define DYNAMIC_MAC_TABLE_SRC_PORT 0x07000000
#define DYNAMIC_MAC_TABLE_TIMESTAMP 0x18000000
#define DYNAMIC_MAC_TABLE_ENTRIES 0xE0000000
#define DYNAMIC_MAC_TABLE_NOT_READY 0x80
#define DYNAMIC_MAC_TABLE_ENTRIES_H 0x7F
#define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x80
#define DYNAMIC_MAC_FID_S 16
#define DYNAMIC_MAC_SRC_PORT_S 24
#define DYNAMIC_MAC_TIMESTAMP_S 27
#define DYNAMIC_MAC_ENTRIES_S 29
#define DYNAMIC_MAC_ENTRIES_H_S 3
/** /**
* MIB_COUNTER_VALUE 00-00000000-3FFFFFFF * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
* MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF
...@@ -956,9 +874,6 @@ ...@@ -956,9 +874,6 @@
* MIB_COUNTER_OVERFLOW 00-00000040-00000000 * MIB_COUNTER_OVERFLOW 00-00000040-00000000
*/ */
#define MIB_COUNTER_OVERFLOW BIT(6)
#define MIB_COUNTER_VALID BIT(5)
#define MIB_COUNTER_VALUE 0x3FFFFFFF #define MIB_COUNTER_VALUE 0x3FFFFFFF
#define KS_MIB_TOTAL_RX_0 0x100 #define KS_MIB_TOTAL_RX_0 0x100
......
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