Commit a0255a76 authored by Nathan Fontenot's avatar Nathan Fontenot Committed by Shuah Khan

cpupower: Add CPUPOWER_CAP_AMD_HW_PSTATE cpuid caps flag

Add a check in get_cpu_info() for the ability to read frequencies
from hardware and set the CPUPOWER_CAP_AMD_HW_PSTATE cpuid flag.
The cpuid flag is set when CPUID_80000007_EDX[7] is set,
which is all families >= 10h. The check excludes family 14h
because HW pstate reporting was not implemented on family 14h.

This is intended to reduce family checks in the main code paths.
Signed-off-by: default avatarNathan Fontenot <nathan.fontenot@amd.com>
Reviewed-by: default avatarRobert Richter <rrichter@amd.com>
Reviewed-by: skhan@linuxfoundation.org
Signed-off-by: default avatarShuah Khan <skhan@linuxfoundation.org>
parent 7a136a8f
...@@ -94,11 +94,10 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family, ...@@ -94,11 +94,10 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family,
union core_pstate pstate; union core_pstate pstate;
unsigned long long val; unsigned long long val;
/* Only read out frequencies from HW when CPU might be boostable /* Only read out frequencies from HW if HW Pstate is supported,
to keep the code as short and clean as possible. * otherwise frequencies are exported via ACPI tables.
Otherwise frequencies are exported via ACPI tables. */
*/ if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_HW_PSTATE))
if (cpu_family < 0x10 || cpu_family == 0x14)
return -1; return -1;
if (read_msr(cpu, MSR_AMD_PSTATE_LIMIT, &val)) if (read_msr(cpu, MSR_AMD_PSTATE_LIMIT, &val))
......
...@@ -128,9 +128,15 @@ int get_cpu_info(struct cpupower_cpu_info *cpu_info) ...@@ -128,9 +128,15 @@ int get_cpu_info(struct cpupower_cpu_info *cpu_info)
/* AMD or Hygon Boost state enable/disable register */ /* AMD or Hygon Boost state enable/disable register */
if (cpu_info->vendor == X86_VENDOR_AMD || if (cpu_info->vendor == X86_VENDOR_AMD ||
cpu_info->vendor == X86_VENDOR_HYGON) { cpu_info->vendor == X86_VENDOR_HYGON) {
if (ext_cpuid_level >= 0x80000007 && if (ext_cpuid_level >= 0x80000007) {
(cpuid_edx(0x80000007) & (1 << 9))) if (cpuid_edx(0x80000007) & (1 << 9))
cpu_info->caps |= CPUPOWER_CAP_AMD_CPB; cpu_info->caps |= CPUPOWER_CAP_AMD_CPB;
if ((cpuid_edx(0x80000007) & (1 << 7)) &&
cpu_info->family != 0x14)
/* HW pstate was not implemented in family 0x14 */
cpu_info->caps |= CPUPOWER_CAP_AMD_HW_PSTATE;
}
if (ext_cpuid_level >= 0x80000008 && if (ext_cpuid_level >= 0x80000008 &&
cpuid_ebx(0x80000008) & (1 << 4)) cpuid_ebx(0x80000008) & (1 << 4))
......
...@@ -70,6 +70,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL, ...@@ -70,6 +70,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
#define CPUPOWER_CAP_IS_SNB 0x00000020 #define CPUPOWER_CAP_IS_SNB 0x00000020
#define CPUPOWER_CAP_INTEL_IDA 0x00000040 #define CPUPOWER_CAP_INTEL_IDA 0x00000040
#define CPUPOWER_CAP_AMD_RDPRU 0x00000080 #define CPUPOWER_CAP_AMD_RDPRU 0x00000080
#define CPUPOWER_CAP_AMD_HW_PSTATE 0x00000100
#define CPUPOWER_AMD_CPBDIS 0x02000000 #define CPUPOWER_AMD_CPBDIS 0x02000000
......
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