Commit a03dc368 authored by Anjali Singhai Jain's avatar Anjali Singhai Jain Committed by Jeff Kirsher

i40e/i40evf: Fix an accidental error with BIT_ULL replacement

A mask value of 0x1FF was accidentally replaced with a bit mask
causing flow director sideband to be broken.

Change-ID: Id3387f67dd1b567b41692b570b383c58671e1eae
Signed-off-by: default avatarAnjali Singhai Jain <anjali.singhai@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 8589af70
...@@ -1068,8 +1068,8 @@ enum i40e_filter_program_desc_fd_status { ...@@ -1068,8 +1068,8 @@ enum i40e_filter_program_desc_fd_status {
}; };
#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \ #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
......
...@@ -1055,8 +1055,8 @@ enum i40e_filter_program_desc_fd_status { ...@@ -1055,8 +1055,8 @@ enum i40e_filter_program_desc_fd_status {
}; };
#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \ #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment