Commit a1571f1f authored by Fabien Parent's avatar Fabien Parent Committed by Ulf Hansson
parent 0cd3f86a
...@@ -31,6 +31,7 @@ properties: ...@@ -31,6 +31,7 @@ properties:
- mediatek,mt8188-power-controller - mediatek,mt8188-power-controller
- mediatek,mt8192-power-controller - mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller - mediatek,mt8195-power-controller
- mediatek,mt8365-power-controller
'#power-domain-cells': '#power-domain-cells':
const: 1 const: 1
...@@ -88,6 +89,7 @@ $defs: ...@@ -88,6 +89,7 @@ $defs:
"include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain. "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
"include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
maxItems: 1 maxItems: 1
clocks: clocks:
...@@ -115,6 +117,10 @@ $defs: ...@@ -115,6 +117,10 @@ $defs:
$ref: /schemas/types.yaml#/definitions/phandle $ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the INFRACFG register range. description: phandle to the device containing the INFRACFG register range.
mediatek,infracfg-nao:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the INFRACFG-NAO register range.
mediatek,smi: mediatek,smi:
$ref: /schemas/types.yaml#/definitions/phandle $ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the SMI register range. description: phandle to the device containing the SMI register range.
......
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2022 MediaTek Inc.
*/
#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H
#define _DT_BINDINGS_POWER_MT8365_POWER_H
#define MT8365_POWER_DOMAIN_MM 0
#define MT8365_POWER_DOMAIN_CONN 1
#define MT8365_POWER_DOMAIN_MFG 2
#define MT8365_POWER_DOMAIN_AUDIO 3
#define MT8365_POWER_DOMAIN_CAM 4
#define MT8365_POWER_DOMAIN_DSP 5
#define MT8365_POWER_DOMAIN_VDEC 6
#define MT8365_POWER_DOMAIN_VENC 7
#define MT8365_POWER_DOMAIN_APU 8
#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */
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