Commit a2163cc3 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: mite: tidy up kernel messages in mite_steup()

The dev_err() messages with pci_ioremap_bar() fails are just noise.
Remove them.

The 'use_win1' and 'fifo_size' dev_info() messages are also noise
but they may be useful when debugging. Change them to dev_dbg().

Absorb dump_chip_signnature() and change the pr_info() messages
to dev_dbg(). These also might be useful when debugging.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 48f2c1ae
...@@ -219,23 +219,6 @@ static void mite_dma_reset(struct mite_channel *mite_chan) ...@@ -219,23 +219,6 @@ static void mite_dma_reset(struct mite_channel *mite_chan)
mite_chan->mite->mmio + MITE_CHOR(mite_chan->channel)); mite_chan->mite->mmio + MITE_CHOR(mite_chan->channel));
} }
static void dump_chip_signature(u32 csigr_bits)
{
unsigned int wpdep;
/* get the wpdep bits and convert it to the write port fifo depth */
wpdep = CSIGR_TO_WPDEP(csigr_bits);
if (wpdep)
wpdep = BIT(wpdep);
pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
CSIGR_TO_VER(csigr_bits), CSIGR_TO_TYPE(csigr_bits),
CSIGR_TO_MMODE(csigr_bits), CSIGR_TO_IMODE(csigr_bits));
pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
CSIGR_TO_DMAC(csigr_bits), wpdep,
CSIGR_TO_WINS(csigr_bits), CSIGR_TO_IOWINS(csigr_bits));
}
static unsigned int mite_fifo_size(struct mite *mite, unsigned int channel) static unsigned int mite_fifo_size(struct mite *mite, unsigned int channel)
{ {
unsigned int fcr_bits = readl(mite->mmio + MITE_FCR(channel)); unsigned int fcr_bits = readl(mite->mmio + MITE_FCR(channel));
...@@ -739,29 +722,24 @@ static int mite_setup(struct comedi_device *dev, struct mite *mite, ...@@ -739,29 +722,24 @@ static int mite_setup(struct comedi_device *dev, struct mite *mite,
int i; int i;
u32 csigr_bits; u32 csigr_bits;
unsigned int unknown_dma_burst_bits; unsigned int unknown_dma_burst_bits;
unsigned int wpdep;
pci_set_master(mite->pcidev); pci_set_master(mite->pcidev);
mite->mmio = pci_ioremap_bar(mite->pcidev, 0); mite->mmio = pci_ioremap_bar(mite->pcidev, 0);
if (!mite->mmio) { if (!mite->mmio)
dev_err(dev->class_dev,
"Failed to remap mite io memory address\n");
return -ENOMEM; return -ENOMEM;
}
dev->mmio = pci_ioremap_bar(mite->pcidev, 1); dev->mmio = pci_ioremap_bar(mite->pcidev, 1);
if (!dev->mmio) { if (!dev->mmio)
dev_err(dev->class_dev,
"Failed to remap daq io memory address\n");
return -ENOMEM; return -ENOMEM;
}
daq_phys_addr = pci_resource_start(mite->pcidev, 1); daq_phys_addr = pci_resource_start(mite->pcidev, 1);
length = pci_resource_len(mite->pcidev, 1); length = pci_resource_len(mite->pcidev, 1);
if (use_win1) { if (use_win1) {
writel(0, mite->mmio + MITE_IODWBSR); writel(0, mite->mmio + MITE_IODWBSR);
dev_info(dev->class_dev, dev_dbg(dev->class_dev,
"using I/O Window Base Size register 1\n"); "mite: using I/O Window Base Size register 1\n");
writel(daq_phys_addr | WENAB | writel(daq_phys_addr | WENAB |
MITE_IODWBSR_1_WSIZE_bits(length), MITE_IODWBSR_1_WSIZE_bits(length),
mite->mmio + MITE_IODWBSR_1); mite->mmio + MITE_IODWBSR_1);
...@@ -792,7 +770,21 @@ static int mite_setup(struct comedi_device *dev, struct mite *mite, ...@@ -792,7 +770,21 @@ static int mite_setup(struct comedi_device *dev, struct mite *mite,
mite->num_channels, MAX_MITE_DMA_CHANNELS); mite->num_channels, MAX_MITE_DMA_CHANNELS);
mite->num_channels = MAX_MITE_DMA_CHANNELS; mite->num_channels = MAX_MITE_DMA_CHANNELS;
} }
dump_chip_signature(csigr_bits);
/* get the wpdep bits and convert it to the write port fifo depth */
wpdep = CSIGR_TO_WPDEP(csigr_bits);
if (wpdep)
wpdep = BIT(wpdep);
dev_dbg(dev->class_dev,
"mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n",
CSIGR_TO_VER(csigr_bits), CSIGR_TO_TYPE(csigr_bits),
CSIGR_TO_MMODE(csigr_bits), CSIGR_TO_IMODE(csigr_bits));
dev_dbg(dev->class_dev,
"mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
CSIGR_TO_DMAC(csigr_bits), wpdep,
CSIGR_TO_WINS(csigr_bits), CSIGR_TO_IOWINS(csigr_bits));
for (i = 0; i < mite->num_channels; i++) { for (i = 0; i < mite->num_channels; i++) {
writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i)); writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i));
/* disable interrupts */ /* disable interrupts */
...@@ -802,7 +794,7 @@ static int mite_setup(struct comedi_device *dev, struct mite *mite, ...@@ -802,7 +794,7 @@ static int mite_setup(struct comedi_device *dev, struct mite *mite,
mite->mmio + MITE_CHCR(i)); mite->mmio + MITE_CHCR(i));
} }
mite->fifo_size = mite_fifo_size(mite, 0); mite->fifo_size = mite_fifo_size(mite, 0);
dev_info(dev->class_dev, "fifo size is %i.\n", mite->fifo_size); dev_dbg(dev->class_dev, "mite: fifo size is %i.\n", mite->fifo_size);
return 0; return 0;
} }
......
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