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Commit a2bb28a0 authored by Tony Lindgren's avatar Tony Lindgren
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Merge branch 'omap7xx-fortony-rc3' of git://robotfuzz.com/linwizard-kernel into omap7xx

parents 012abeea f8631e7b
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Showing with 480 additions and 680 deletions
arch/arm/mach-omap1/board-fsample.c
View file @ a2bb28a0
......@@ -107,7 +107,7 @@ static struct resource smc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_730_MPU_EXT_NIRQ,
.start = INT_7XX_MPU_EXT_NIRQ,
.end = 0,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
......@@ -196,8 +196,8 @@ static struct platform_device smc91x_device = {
static struct resource kp_resources[] = {
[0] = {
.start = INT_730_MPUIO_KEYPAD,
.end = INT_730_MPUIO_KEYPAD,
.start = INT_7XX_MPUIO_KEYPAD,
.end = INT_7XX_MPUIO_KEYPAD,
.flags = IORESOURCE_IRQ,
},
};
......@@ -309,7 +309,7 @@ static void __init omap_fsample_map_io(void)
/*
* Hold GSM Reset until needed
*/
omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
/*
* UARTs -> done automagically by 8250 driver
......@@ -320,21 +320,21 @@ static void __init omap_fsample_map_io(void)
*/
/* Flash: CS0 timings setup */
omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
/*
* Ethernet support through the debug board
* CS1 timings setup
*/
omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
/*
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
* It is used as the Ethernet controller interrupt
*/
omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
}
MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
......
arch/arm/mach-omap1/board-perseus2.c
View file @ a2bb28a0
......@@ -74,7 +74,7 @@ static struct resource smc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_730_MPU_EXT_NIRQ,
.start = INT_7XX_MPU_EXT_NIRQ,
.end = 0,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
......@@ -163,8 +163,8 @@ static struct platform_device smc91x_device = {
static struct resource kp_resources[] = {
[0] = {
.start = INT_730_MPUIO_KEYPAD,
.end = INT_730_MPUIO_KEYPAD,
.start = INT_7XX_MPUIO_KEYPAD,
.end = INT_7XX_MPUIO_KEYPAD,
.flags = IORESOURCE_IRQ,
},
};
......@@ -270,7 +270,7 @@ static void __init omap_perseus2_map_io(void)
/*
* Hold GSM Reset until needed
*/
omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
/*
* UARTs -> done automagically by 8250 driver
......@@ -281,21 +281,21 @@ static void __init omap_perseus2_map_io(void)
*/
/* Flash: CS0 timings setup */
omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
/*
* Ethernet support through the debug board
* CS1 timings setup
*/
omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
/*
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
* It is used as the Ethernet controller interrupt
*/
omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
}
MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
......
arch/arm/mach-omap1/clock.c
View file @ a2bb28a0
......@@ -69,13 +69,13 @@ struct omap_clk {
}
#define CK_310 (1 << 0)
#define CK_730 (1 << 1)
#define CK_7XX (1 << 1)
#define CK_1510 (1 << 2)
#define CK_16XX (1 << 3)
static struct omap_clk omap_clks[] = {
/* non-ULPD clocks */
CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310),
/* CK_GEN1 clocks */
CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
......@@ -83,7 +83,7 @@ static struct omap_clk omap_clks[] = {
CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
......@@ -97,7 +97,7 @@ static struct omap_clk omap_clks[] = {
CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
/* CK_GEN3 clocks */
CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730),
CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX),
CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
......@@ -108,7 +108,7 @@ static struct omap_clk omap_clks[] = {
CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730),
CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
/* ULPD clocks */
CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
......@@ -398,7 +398,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
* Reprogramming the DPLL is tricky, it must be done from SRAM.
* (on 730, bit 13 must always be 1)
*/
if (cpu_is_omap730())
if (cpu_is_omap7xx())
omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
else
omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
......@@ -783,8 +783,8 @@ int __init omap1_clk_init(void)
cpu_mask |= CK_16XX;
if (cpu_is_omap1510())
cpu_mask |= CK_1510;
if (cpu_is_omap730())
cpu_mask |= CK_730;
if (cpu_is_omap7xx())
cpu_mask |= CK_7XX;
if (cpu_is_omap310())
cpu_mask |= CK_310;
......@@ -800,7 +800,7 @@ int __init omap1_clk_init(void)
crystal_type = info->system_clock_type;
}
#if defined(CONFIG_ARCH_OMAP730)
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
ck_ref.rate = 13000000;
#elif defined(CONFIG_ARCH_OMAP16XX)
if (crystal_type == 2)
......@@ -847,7 +847,7 @@ int __init omap1_clk_init(void)
printk(KERN_ERR "System frequencies not set. Check your config.\n");
/* Guess sane values (60MHz) */
omap_writew(0x2290, DPLL_CTL);
omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
ck_dpll1.rate = 60000000;
}
#endif
......@@ -862,7 +862,7 @@ int __init omap1_clk_init(void)
#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
/* Select slicer output as OMAP input clock */
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
#endif
/* Amstrad Delta wants BCLK high when inactive */
......@@ -873,7 +873,7 @@ int __init omap1_clk_init(void)
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
/* (on 730, bit 13 must not be cleared) */
if (cpu_is_omap730())
if (cpu_is_omap7xx())
omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
else
omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
......
arch/arm/mach-omap1/io.c
View file @ a2bb28a0
......@@ -36,33 +36,17 @@ static struct map_desc omap_io_desc[] __initdata = {
}
};
#ifdef CONFIG_ARCH_OMAP730
static struct map_desc omap730_io_desc[] __initdata = {
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
static struct map_desc omap7xx_io_desc[] __initdata = {
{
.virtual = OMAP730_DSP_BASE,
.pfn = __phys_to_pfn(OMAP730_DSP_START),
.length = OMAP730_DSP_SIZE,
.virtual = OMAP7XX_DSP_BASE,
.pfn = __phys_to_pfn(OMAP7XX_DSP_START),
.length = OMAP7XX_DSP_SIZE,
.type = MT_DEVICE
}, {
.virtual = OMAP730_DSPREG_BASE,
.pfn = __phys_to_pfn(OMAP730_DSPREG_START),
.length = OMAP730_DSPREG_SIZE,
.type = MT_DEVICE
}
};
#endif
#ifdef CONFIG_ARCH_OMAP850
static struct map_desc omap850_io_desc[] __initdata = {
{
.virtual = OMAP850_DSP_BASE,
.pfn = __phys_to_pfn(OMAP850_DSP_START),
.length = OMAP850_DSP_SIZE,
.type = MT_DEVICE
}, {
.virtual = OMAP850_DSPREG_BASE,
.pfn = __phys_to_pfn(OMAP850_DSPREG_START),
.length = OMAP850_DSPREG_SIZE,
.virtual = OMAP7XX_DSPREG_BASE,
.pfn = __phys_to_pfn(OMAP7XX_DSPREG_START),
.length = OMAP7XX_DSPREG_SIZE,
.type = MT_DEVICE
}
};
......@@ -120,18 +104,11 @@ void __init omap1_map_common_io(void)
*/
omap_check_revision();
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730()) {
iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
}
#endif
#ifdef CONFIG_ARCH_OMAP850
if (cpu_is_omap850()) {
iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc));
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
if (cpu_is_omap7xx()) {
iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap15xx()) {
iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
......
arch/arm/mach-omap1/irq.c
View file @ a2bb28a0
......@@ -137,16 +137,8 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
irq_bank_writel(val, bank, offset);
}
#ifdef CONFIG_ARCH_OMAP730
static struct omap_irq_bank omap730_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
};
#endif
#ifdef CONFIG_ARCH_OMAP850
static struct omap_irq_bank omap850_irq_banks[] = {
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
static struct omap_irq_bank omap7xx_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
......@@ -186,16 +178,10 @@ void __init omap_init_irq(void)
{
int i, j;
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730()) {
irq_banks = omap730_irq_banks;
irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP850
if (cpu_is_omap850()) {
irq_banks = omap850_irq_banks;
irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
if (cpu_is_omap7xx()) {
irq_banks = omap7xx_irq_banks;
irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
......@@ -247,10 +233,8 @@ void __init omap_init_irq(void)
/* Unmask level 2 handler */
if (cpu_is_omap730())
omap_unmask_irq(INT_730_IH2_IRQ);
else if (cpu_is_omap850())
omap_unmask_irq(INT_850_IH2_IRQ);
if (cpu_is_omap7xx())
omap_unmask_irq(INT_7XX_IH2_IRQ);
else if (cpu_is_omap15xx())
omap_unmask_irq(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
......
arch/arm/mach-omap1/mcbsp.c
View file @ a2bb28a0
......@@ -79,29 +79,29 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
.free = omap1_mcbsp_free,
};
#ifdef CONFIG_ARCH_OMAP730
static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
{
.phys_base = OMAP730_MCBSP1_BASE,
.phys_base = OMAP7XX_MCBSP1_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
.rx_irq = INT_730_McBSP1RX,
.tx_irq = INT_730_McBSP1TX,
.rx_irq = INT_7XX_McBSP1RX,
.tx_irq = INT_7XX_McBSP1TX,
.ops = &omap1_mcbsp_ops,
},
{
.phys_base = OMAP730_MCBSP2_BASE,
.phys_base = OMAP7XX_MCBSP2_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
.rx_irq = INT_730_McBSP2RX,
.tx_irq = INT_730_McBSP2TX,
.rx_irq = INT_7XX_McBSP2RX,
.tx_irq = INT_7XX_McBSP2TX,
.ops = &omap1_mcbsp_ops,
},
};
#define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata)
#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata)
#else
#define omap730_mcbsp_pdata NULL
#define OMAP730_MCBSP_PDATA_SZ 0
#define omap7xx_mcbsp_pdata NULL
#define OMAP7XX_MCBSP_PDATA_SZ 0
#endif
#ifdef CONFIG_ARCH_OMAP15XX
......@@ -172,8 +172,8 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
int __init omap1_mcbsp_init(void)
{
if (cpu_is_omap730())
omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
if (cpu_is_omap7xx())
omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
if (cpu_is_omap15xx())
omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
if (cpu_is_omap16xx())
......@@ -184,9 +184,9 @@ int __init omap1_mcbsp_init(void)
if (!mcbsp_ptr)
return -ENOMEM;
if (cpu_is_omap730())
omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
OMAP730_MCBSP_PDATA_SZ);
if (cpu_is_omap7xx())
omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
OMAP7XX_MCBSP_PDATA_SZ);
if (cpu_is_omap15xx())
omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
......
arch/arm/mach-omap1/mux.c
View file @ a2bb28a0
......@@ -35,47 +35,28 @@
static struct omap_mux_cfg arch_mux_cfg;
#ifdef CONFIG_ARCH_OMAP730
static struct pin_config __initdata_or_module omap730_pins[] = {
MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0)
MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0)
MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0)
MUX_CFG_730("F3_730_KBR3", 13, 1, 0, 0, 1, 0)
MUX_CFG_730("D2_730_KBR4", 13, 5, 0, 4, 1, 0)
MUX_CFG_730("C2_730_KBC0", 13, 9, 0, 8, 1, 0)
MUX_CFG_730("D3_730_KBC1", 13, 13, 0, 12, 1, 0)
MUX_CFG_730("E4_730_KBC2", 13, 17, 0, 16, 1, 0)
MUX_CFG_730("F4_730_KBC3", 13, 21, 0, 20, 1, 0)
MUX_CFG_730("E3_730_KBC4", 13, 25, 0, 24, 1, 0)
MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0)
MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0)
MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0)
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
static struct pin_config __initdata_or_module omap7xx_pins[] = {
MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0)
MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0)
MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0)
MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0)
MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0)
MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0)
MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0)
};
#define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins)
#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
#else
#define omap730_pins NULL
#define OMAP730_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP730 */
#ifdef CONFIG_ARCH_OMAP850
struct pin_config __initdata_or_module omap850_pins[] = {
MUX_CFG_850("E2_850_KBR0", 12, 21, 0, 20, 1, 0)
MUX_CFG_850("J7_850_KBR1", 12, 25, 0, 24, 1, 0)
MUX_CFG_850("E1_850_KBR2", 12, 29, 0, 28, 1, 0)
MUX_CFG_850("F3_850_KBR3", 13, 1, 0, 0, 1, 0)
MUX_CFG_850("D2_850_KBR4", 13, 5, 0, 4, 1, 0)
MUX_CFG_850("C2_850_KBC0", 13, 9, 0, 8, 1, 0)
MUX_CFG_850("D3_850_KBC1", 13, 13, 0, 12, 1, 0)
MUX_CFG_850("E4_850_KBC2", 13, 17, 0, 16, 1, 0)
MUX_CFG_850("F4_850_KBC3", 13, 21, 0, 20, 1, 0)
MUX_CFG_850("E3_850_KBC4", 13, 25, 0, 24, 1, 0)
MUX_CFG_850("AA17_850_USB_DM", 2, 21, 0, 20, 0, 0)
MUX_CFG_850("W16_850_USB_PU_EN", 2, 25, 0, 24, 0, 0)
MUX_CFG_850("W17_850_USB_VBUSI", 2, 29, 0, 28, 0, 0)
};
#endif
#define omap7xx_pins NULL
#define OMAP7XX_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static struct pin_config __initdata_or_module omap1xxx_pins[] = {
......@@ -438,11 +419,6 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pull_name, cfg->pull_reg, pull_orig, pull);
}
#ifdef CONFIG_ARCH_OMAP850
omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins));
#endif
#endif
#ifdef CONFIG_OMAP_MUX_ERRORS
......@@ -454,9 +430,9 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
int __init omap1_mux_init(void)
{
if (cpu_is_omap730()) {
arch_mux_cfg.pins = omap730_pins;
arch_mux_cfg.size = OMAP730_PINS_SZ;
if (cpu_is_omap7xx()) {
arch_mux_cfg.pins = omap7xx_pins;
arch_mux_cfg.size = OMAP7XX_PINS_SZ;
arch_mux_cfg.cfg_reg = omap1_cfg_reg;
}
......
arch/arm/mach-omap1/pm.c
View file @ a2bb28a0
......@@ -62,7 +62,7 @@
static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
......@@ -183,9 +183,9 @@ static void omap_pm_wakeup_setup(void)
* drivers must still separately call omap_set_gpio_wakeup() to
* wake up to a GPIO interrupt.
*/
if (cpu_is_omap730())
level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_730_IH2_IRQ);
if (cpu_is_omap7xx())
level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
else if (cpu_is_omap15xx())
level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
......@@ -195,10 +195,10 @@ static void omap_pm_wakeup_setup(void)
omap_writel(~level1_wake, OMAP_IH1_MIR);
if (cpu_is_omap730()) {
if (cpu_is_omap7xx()) {
omap_writel(~level2_wake, OMAP_IH2_0_MIR);
omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
OMAP_IH2_1_MIR);
} else if (cpu_is_omap15xx()) {
level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
......@@ -253,15 +253,15 @@ void omap1_pm_suspend(void)
* Save interrupt, MPUI, ARM and UPLD control registers.
*/
if (cpu_is_omap730()) {
MPUI730_SAVE(OMAP_IH1_MIR);
MPUI730_SAVE(OMAP_IH2_0_MIR);
MPUI730_SAVE(OMAP_IH2_1_MIR);
MPUI730_SAVE(MPUI_CTRL);
MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI730_SAVE(MPUI_DSP_API_CONFIG);
MPUI730_SAVE(EMIFS_CONFIG);
MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
if (cpu_is_omap7xx()) {
MPUI7XX_SAVE(OMAP_IH1_MIR);
MPUI7XX_SAVE(OMAP_IH2_0_MIR);
MPUI7XX_SAVE(OMAP_IH2_1_MIR);
MPUI7XX_SAVE(MPUI_CTRL);
MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
MPUI7XX_SAVE(EMIFS_CONFIG);
MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
} else if (cpu_is_omap15xx()) {
MPUI1510_SAVE(OMAP_IH1_MIR);
......@@ -306,7 +306,7 @@ void omap1_pm_suspend(void)
omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
/* shut down dsp_ck */
if (!cpu_is_omap730())
if (!cpu_is_omap7xx())
omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
/* temporarily enabling api_ck to access DSP registers */
......@@ -383,12 +383,12 @@ void omap1_pm_suspend(void)
ULPD_RESTORE(ULPD_CLOCK_CTRL);
ULPD_RESTORE(ULPD_STATUS_REQ);
if (cpu_is_omap730()) {
MPUI730_RESTORE(EMIFS_CONFIG);
MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
MPUI730_RESTORE(OMAP_IH1_MIR);
MPUI730_RESTORE(OMAP_IH2_0_MIR);
MPUI730_RESTORE(OMAP_IH2_1_MIR);
if (cpu_is_omap7xx()) {
MPUI7XX_RESTORE(EMIFS_CONFIG);
MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
MPUI7XX_RESTORE(OMAP_IH1_MIR);
MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
} else if (cpu_is_omap15xx()) {
MPUI1510_RESTORE(MPUI_CTRL);
MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
......@@ -461,13 +461,13 @@ static int omap_pm_read_proc(
ULPD_SAVE(ULPD_DPLL_CTRL);
ULPD_SAVE(ULPD_POWER_CTRL);
if (cpu_is_omap730()) {
MPUI730_SAVE(MPUI_CTRL);
MPUI730_SAVE(MPUI_DSP_STATUS);
MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI730_SAVE(MPUI_DSP_API_CONFIG);
MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
MPUI730_SAVE(EMIFS_CONFIG);
if (cpu_is_omap7xx()) {
MPUI7XX_SAVE(MPUI_CTRL);
MPUI7XX_SAVE(MPUI_DSP_STATUS);
MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
MPUI7XX_SAVE(EMIFS_CONFIG);
} else if (cpu_is_omap15xx()) {
MPUI1510_SAVE(MPUI_CTRL);
MPUI1510_SAVE(MPUI_DSP_STATUS);
......@@ -517,20 +517,20 @@ static int omap_pm_read_proc(
ULPD_SHOW(ULPD_STATUS_REQ),
ULPD_SHOW(ULPD_POWER_CTRL));
if (cpu_is_omap730()) {
if (cpu_is_omap7xx()) {
my_buffer_offset += sprintf(my_base + my_buffer_offset,
"MPUI730_CTRL_REG 0x%-8x \n"
"MPUI730_DSP_STATUS_REG: 0x%-8x \n"
"MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
"MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
"MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
"MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
MPUI730_SHOW(MPUI_CTRL),
MPUI730_SHOW(MPUI_DSP_STATUS),
MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
MPUI730_SHOW(MPUI_DSP_API_CONFIG),
MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
MPUI730_SHOW(EMIFS_CONFIG));
"MPUI7XX_CTRL_REG 0x%-8x \n"
"MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
"MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
"MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
"MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
"MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
MPUI7XX_SHOW(MPUI_CTRL),
MPUI7XX_SHOW(MPUI_DSP_STATUS),
MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
MPUI7XX_SHOW(EMIFS_CONFIG));
} else if (cpu_is_omap15xx()) {
my_buffer_offset += sprintf(my_base + my_buffer_offset,
"MPUI1510_CTRL_REG 0x%-8x \n"
......@@ -668,9 +668,9 @@ static int __init omap_pm_init(void)
* These routines need to be in SRAM as that's the only
* memory the MPU can see when it wakes up.
*/
if (cpu_is_omap730()) {
omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
omap730_cpu_suspend_sz);
if (cpu_is_omap7xx()) {
omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
omap7xx_cpu_suspend_sz);
} else if (cpu_is_omap15xx()) {
omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
omap1510_cpu_suspend_sz);
......@@ -686,8 +686,8 @@ static int __init omap_pm_init(void)
pm_idle = omap1_pm_idle;
if (cpu_is_omap730())
setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
if (cpu_is_omap7xx())
setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
else if (cpu_is_omap16xx())
setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
......@@ -700,8 +700,8 @@ static int __init omap_pm_init(void)
omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
/* Configure IDLECT3 */
if (cpu_is_omap730())
omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
if (cpu_is_omap7xx())
omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
else if (cpu_is_omap16xx())
omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
......
arch/arm/mach-omap1/pm.h
View file @ a2bb28a0
......@@ -98,13 +98,14 @@
#define OMAP1610_IDLECT3 0xfffece24
#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7
#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7
#define OMAP730_IDLECT3_VAL 0x3f
#define OMAP730_IDLECT3 0xfffece24
#define OMAP730_IDLE_LOOP_REQUEST 0x0C00
#define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7
#define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7
#define OMAP7XX_IDLECT3_VAL 0x3f
#define OMAP7XX_IDLECT3 0xfffece24
#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00
#if !defined(CONFIG_ARCH_OMAP730) && \
!defined(CONFIG_ARCH_OMAP850) && \
!defined(CONFIG_ARCH_OMAP15XX) && \
!defined(CONFIG_ARCH_OMAP16XX)
#warning "Power management for this processor not implemented yet"
......@@ -122,17 +123,17 @@ extern void allow_idle_sleep(void);
extern void omap1_pm_idle(void);
extern void omap1_pm_suspend(void);
extern void omap730_cpu_suspend(unsigned short, unsigned short);
extern void omap7xx_cpu_suspend(unsigned short, unsigned short);
extern void omap1510_cpu_suspend(unsigned short, unsigned short);
extern void omap1610_cpu_suspend(unsigned short, unsigned short);
extern void omap730_idle_loop_suspend(void);
extern void omap7xx_idle_loop_suspend(void);
extern void omap1510_idle_loop_suspend(void);
extern void omap1610_idle_loop_suspend(void);
extern unsigned int omap730_cpu_suspend_sz;
extern unsigned int omap7xx_cpu_suspend_sz;
extern unsigned int omap1510_cpu_suspend_sz;
extern unsigned int omap1610_cpu_suspend_sz;
extern unsigned int omap730_idle_loop_suspend_sz;
extern unsigned int omap7xx_idle_loop_suspend_sz;
extern unsigned int omap1510_idle_loop_suspend_sz;
extern unsigned int omap1610_idle_loop_suspend_sz;
......@@ -155,9 +156,9 @@ extern void omap_serial_wake_trigger(int enable);
#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
......@@ -232,24 +233,24 @@ enum mpui1510_save_state {
#endif
};
enum mpui730_save_state {
MPUI730_SLEEP_SAVE_START = 0,
enum mpui7xx_save_state {
MPUI7XX_SLEEP_SAVE_START = 0,
/*
* MPUI registers 32 bits
*/
MPUI730_SLEEP_SAVE_MPUI_CTRL,
MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
#if defined(CONFIG_ARCH_OMAP730)
MPUI730_SLEEP_SAVE_SIZE
MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
MPUI7XX_SLEEP_SAVE_SIZE
#else
MPUI730_SLEEP_SAVE_SIZE = 0
MPUI7XX_SLEEP_SAVE_SIZE = 0
#endif
};
......
arch/arm/mach-omap1/serial.c
View file @ a2bb28a0
......@@ -110,18 +110,11 @@ void __init omap_serial_init(void)
{
int i;
if (cpu_is_omap730()) {
if (cpu_is_omap7xx()) {
serial_platform_data[0].regshift = 0;
serial_platform_data[1].regshift = 0;
serial_platform_data[0].irq = INT_730_UART_MODEM_1;
serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
}
if (cpu_is_omap850()) {
serial_platform_data[0].regshift = 0;
serial_platform_data[1].regshift = 0;
serial_platform_data[0].irq = INT_850_UART_MODEM_1;
serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2;
serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
}
if (cpu_is_omap15xx()) {
......
arch/arm/mach-omap1/sleep.S
View file @ a2bb28a0
/*
* linux/arch/arm/mach-omap1/sleep.S
*
* Low-level OMAP730/1510/1610 sleep/wakeUp support
* Low-level OMAP7XX/1510/1610 sleep/wakeUp support
*
* Initial SA1110 code:
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
......@@ -57,8 +57,8 @@
*
*/
#if defined(CONFIG_ARCH_OMAP730)
ENTRY(omap730_cpu_suspend)
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
ENTRY(omap7xx_cpu_suspend)
@ save registers on stack
stmfd sp!, {r0 - r12, lr}
......@@ -91,13 +91,13 @@ ENTRY(omap730_cpu_suspend)
@ turn off clock domains
@ do not disable PERCK (0x04)
mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
@ request ARM idle
mov r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff
orr r3, r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff00
mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
@ disable instruction cache
......@@ -113,7 +113,7 @@ ENTRY(omap730_cpu_suspend)
mov r2, #0
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
/*
* omap730_cpu_suspend()'s resume point.
* omap7xx_cpu_suspend()'s resume point.
*
* It will just start executing here, so we'll restore stuff from the
* stack.
......@@ -132,9 +132,9 @@ ENTRY(omap730_cpu_suspend)
@ restore regs and return
ldmfd sp!, {r0 - r12, pc}
ENTRY(omap730_cpu_suspend_sz)
.word . - omap730_cpu_suspend
#endif /* CONFIG_ARCH_OMAP730 */
ENTRY(omap7xx_cpu_suspend_sz)
.word . - omap7xx_cpu_suspend
#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
#ifdef CONFIG_ARCH_OMAP15XX
ENTRY(omap1510_cpu_suspend)
......
arch/arm/plat-omap/devices.c
View file @ a2bb28a0
......@@ -113,17 +113,17 @@ static void omap_init_kp(void)
omap_cfg_reg(E19_1610_KBR4);
omap_cfg_reg(N19_1610_KBR5);
} else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
omap_cfg_reg(E2_730_KBR0);
omap_cfg_reg(J7_730_KBR1);
omap_cfg_reg(E1_730_KBR2);
omap_cfg_reg(F3_730_KBR3);
omap_cfg_reg(D2_730_KBR4);
omap_cfg_reg(C2_730_KBC0);
omap_cfg_reg(D3_730_KBC1);
omap_cfg_reg(E4_730_KBC2);
omap_cfg_reg(F4_730_KBC3);
omap_cfg_reg(E3_730_KBC4);
omap_cfg_reg(E2_7XX_KBR0);
omap_cfg_reg(J7_7XX_KBR1);
omap_cfg_reg(E1_7XX_KBR2);
omap_cfg_reg(F3_7XX_KBR3);
omap_cfg_reg(D2_7XX_KBR4);
omap_cfg_reg(C2_7XX_KBC0);
omap_cfg_reg(D3_7XX_KBC1);
omap_cfg_reg(E4_7XX_KBC2);
omap_cfg_reg(F4_7XX_KBC3);
omap_cfg_reg(E3_7XX_KBC4);
} else if (machine_is_omap_h4()) {
omap_cfg_reg(T19_24XX_KBR0);
omap_cfg_reg(R19_24XX_KBR1);
......
arch/arm/plat-omap/gpio.c
View file @ a2bb28a0
This diff is collapsed.
arch/arm/plat-omap/include/mach/entry-macro.S
View file @ a2bb28a0
......@@ -17,11 +17,11 @@
#if defined(CONFIG_ARCH_OMAP1)
#if defined(CONFIG_ARCH_OMAP730) && \
#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
#error "FIXME: OMAP730 doesn't support multiple-OMAP"
#elif defined(CONFIG_ARCH_OMAP730)
#define INT_IH2_IRQ INT_730_IH2_IRQ
#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
#define INT_IH2_IRQ INT_7XX_IH2_IRQ
#elif defined(CONFIG_ARCH_OMAP15XX)
#define INT_IH2_IRQ INT_1510_IH2_IRQ
#elif defined(CONFIG_ARCH_OMAP16XX)
......
arch/arm/plat-omap/include/mach/hardware.h
View file @ a2bb28a0
......@@ -280,7 +280,7 @@
* ---------------------------------------------------------------------------
*/
#include "omap730.h"
#include "omap7xx.h"
#include "omap1510.h"
#include "omap16xx.h"
#include "omap24xx.h"
......
arch/arm/plat-omap/include/mach/irqs.h
View file @ a2bb28a0
......@@ -86,49 +86,26 @@
#define INT_1610_SSR_FIFO_0 29
/*
* OMAP-730 specific IRQ numbers for interrupt handler 1
* OMAP-7xx specific IRQ numbers for interrupt handler 1
*/
#define INT_730_IH2_FIQ 0
#define INT_730_IH2_IRQ 1
#define INT_730_USB_NON_ISO 2
#define INT_730_USB_ISO 3
#define INT_730_ICR 4
#define INT_730_EAC 5
#define INT_730_GPIO_BANK1 6
#define INT_730_GPIO_BANK2 7
#define INT_730_GPIO_BANK3 8
#define INT_730_McBSP2TX 10
#define INT_730_McBSP2RX 11
#define INT_730_McBSP2RX_OVF 12
#define INT_730_LCD_LINE 14
#define INT_730_GSM_PROTECT 15
#define INT_730_TIMER3 16
#define INT_730_GPIO_BANK5 17
#define INT_730_GPIO_BANK6 18
#define INT_730_SPGIO_WR 29
/*
* OMAP-850 specific IRQ numbers for interrupt handler 1
*/
#define INT_850_IH2_FIQ 0
#define INT_850_IH2_IRQ 1
#define INT_850_USB_NON_ISO 2
#define INT_850_USB_ISO 3
#define INT_850_ICR 4
#define INT_850_EAC 5
#define INT_850_GPIO_BANK1 6
#define INT_850_GPIO_BANK2 7
#define INT_850_GPIO_BANK3 8
#define INT_850_McBSP2TX 10
#define INT_850_McBSP2RX 11
#define INT_850_McBSP2RX_OVF 12
#define INT_850_LCD_LINE 14
#define INT_850_GSM_PROTECT 15
#define INT_850_TIMER3 16
#define INT_850_GPIO_BANK5 17
#define INT_850_GPIO_BANK6 18
#define INT_850_SPGIO_WR 29
#define INT_7XX_IH2_FIQ 0
#define INT_7XX_IH2_IRQ 1
#define INT_7XX_USB_NON_ISO 2
#define INT_7XX_USB_ISO 3
#define INT_7XX_ICR 4
#define INT_7XX_EAC 5
#define INT_7XX_GPIO_BANK1 6
#define INT_7XX_GPIO_BANK2 7
#define INT_7XX_GPIO_BANK3 8
#define INT_7XX_McBSP2TX 10
#define INT_7XX_McBSP2RX 11
#define INT_7XX_McBSP2RX_OVF 12
#define INT_7XX_LCD_LINE 14
#define INT_7XX_GSM_PROTECT 15
#define INT_7XX_TIMER3 16
#define INT_7XX_GPIO_BANK5 17
#define INT_7XX_GPIO_BANK6 18
#define INT_7XX_SPGIO_WR 29
/*
* IRQ numbers for interrupt handler 2
......@@ -206,120 +183,62 @@
#define INT_1610_SHA1MD5 (91 + IH2_BASE)
/*
* OMAP-730 specific IRQ numbers for interrupt handler 2
*/
#define INT_730_HW_ERRORS (0 + IH2_BASE)
#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE)
#define INT_730_CFCD (2 + IH2_BASE)
#define INT_730_CFIREQ (3 + IH2_BASE)
#define INT_730_I2C (4 + IH2_BASE)
#define INT_730_PCC (5 + IH2_BASE)
#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE)
#define INT_730_SPI_100K_1 (7 + IH2_BASE)
#define INT_730_SYREN_SPI (8 + IH2_BASE)
#define INT_730_VLYNQ (9 + IH2_BASE)
#define INT_730_GPIO_BANK4 (10 + IH2_BASE)
#define INT_730_McBSP1TX (11 + IH2_BASE)
#define INT_730_McBSP1RX (12 + IH2_BASE)
#define INT_730_McBSP1RX_OF (13 + IH2_BASE)
#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
#define INT_730_UART_MODEM_1 (15 + IH2_BASE)
#define INT_730_MCSI (16 + IH2_BASE)
#define INT_730_uWireTX (17 + IH2_BASE)
#define INT_730_uWireRX (18 + IH2_BASE)
#define INT_730_SMC_CD (19 + IH2_BASE)
#define INT_730_SMC_IREQ (20 + IH2_BASE)
#define INT_730_HDQ_1WIRE (21 + IH2_BASE)
#define INT_730_TIMER32K (22 + IH2_BASE)
#define INT_730_MMC_SDIO (23 + IH2_BASE)
#define INT_730_UPLD (24 + IH2_BASE)
#define INT_730_USB_HHC_1 (27 + IH2_BASE)
#define INT_730_USB_HHC_2 (28 + IH2_BASE)
#define INT_730_USB_GENI (29 + IH2_BASE)
#define INT_730_USB_OTG (30 + IH2_BASE)
#define INT_730_CAMERA_IF (31 + IH2_BASE)
#define INT_730_RNG (32 + IH2_BASE)
#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
#define INT_730_DBB_RF_EN (34 + IH2_BASE)
#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE)
#define INT_730_SHA1_MD5 (36 + IH2_BASE)
#define INT_730_SPI_100K_2 (37 + IH2_BASE)
#define INT_730_RNG_IDLE (38 + IH2_BASE)
#define INT_730_MPUIO (39 + IH2_BASE)
#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
#define INT_730_LLPC_VSYNC (43 + IH2_BASE)
#define INT_730_WAKE_UP_REQ (46 + IH2_BASE)
#define INT_730_DMA_CH6 (53 + IH2_BASE)
#define INT_730_DMA_CH7 (54 + IH2_BASE)
#define INT_730_DMA_CH8 (55 + IH2_BASE)
#define INT_730_DMA_CH9 (56 + IH2_BASE)
#define INT_730_DMA_CH10 (57 + IH2_BASE)
#define INT_730_DMA_CH11 (58 + IH2_BASE)
#define INT_730_DMA_CH12 (59 + IH2_BASE)
#define INT_730_DMA_CH13 (60 + IH2_BASE)
#define INT_730_DMA_CH14 (61 + IH2_BASE)
#define INT_730_DMA_CH15 (62 + IH2_BASE)
#define INT_730_NAND (63 + IH2_BASE)
/*
* OMAP-850 specific IRQ numbers for interrupt handler 2
* OMAP-7xx specific IRQ numbers for interrupt handler 2
*/
#define INT_850_HW_ERRORS (0 + IH2_BASE)
#define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE)
#define INT_850_CFCD (2 + IH2_BASE)
#define INT_850_CFIREQ (3 + IH2_BASE)
#define INT_850_I2C (4 + IH2_BASE)
#define INT_850_PCC (5 + IH2_BASE)
#define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE)
#define INT_850_SPI_100K_1 (7 + IH2_BASE)
#define INT_850_SYREN_SPI (8 + IH2_BASE)
#define INT_850_VLYNQ (9 + IH2_BASE)
#define INT_850_GPIO_BANK4 (10 + IH2_BASE)
#define INT_850_McBSP1TX (11 + IH2_BASE)
#define INT_850_McBSP1RX (12 + IH2_BASE)
#define INT_850_McBSP1RX_OF (13 + IH2_BASE)
#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
#define INT_850_UART_MODEM_1 (15 + IH2_BASE)
#define INT_850_MCSI (16 + IH2_BASE)
#define INT_850_uWireTX (17 + IH2_BASE)
#define INT_850_uWireRX (18 + IH2_BASE)
#define INT_850_SMC_CD (19 + IH2_BASE)
#define INT_850_SMC_IREQ (20 + IH2_BASE)
#define INT_850_HDQ_1WIRE (21 + IH2_BASE)
#define INT_850_TIMER32K (22 + IH2_BASE)
#define INT_850_MMC_SDIO (23 + IH2_BASE)
#define INT_850_UPLD (24 + IH2_BASE)
#define INT_850_USB_HHC_1 (27 + IH2_BASE)
#define INT_850_USB_HHC_2 (28 + IH2_BASE)
#define INT_850_USB_GENI (29 + IH2_BASE)
#define INT_850_USB_OTG (30 + IH2_BASE)
#define INT_850_CAMERA_IF (31 + IH2_BASE)
#define INT_850_RNG (32 + IH2_BASE)
#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
#define INT_850_DBB_RF_EN (34 + IH2_BASE)
#define INT_850_MPUIO_KEYPAD (35 + IH2_BASE)
#define INT_850_SHA1_MD5 (36 + IH2_BASE)
#define INT_850_SPI_100K_2 (37 + IH2_BASE)
#define INT_850_RNG_IDLE (38 + IH2_BASE)
#define INT_850_MPUIO (39 + IH2_BASE)
#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
#define INT_850_LLPC_OE_RISING (42 + IH2_BASE)
#define INT_850_LLPC_VSYNC (43 + IH2_BASE)
#define INT_850_WAKE_UP_REQ (46 + IH2_BASE)
#define INT_850_DMA_CH6 (53 + IH2_BASE)
#define INT_850_DMA_CH7 (54 + IH2_BASE)
#define INT_850_DMA_CH8 (55 + IH2_BASE)
#define INT_850_DMA_CH9 (56 + IH2_BASE)
#define INT_850_DMA_CH10 (57 + IH2_BASE)
#define INT_850_DMA_CH11 (58 + IH2_BASE)
#define INT_850_DMA_CH12 (59 + IH2_BASE)
#define INT_850_DMA_CH13 (60 + IH2_BASE)
#define INT_850_DMA_CH14 (61 + IH2_BASE)
#define INT_850_DMA_CH15 (62 + IH2_BASE)
#define INT_850_NAND (63 + IH2_BASE)
#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
#define INT_7XX_CFCD (2 + IH2_BASE)
#define INT_7XX_CFIREQ (3 + IH2_BASE)
#define INT_7XX_I2C (4 + IH2_BASE)
#define INT_7XX_PCC (5 + IH2_BASE)
#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
#define INT_7XX_VLYNQ (9 + IH2_BASE)
#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
#define INT_7XX_McBSP1TX (11 + IH2_BASE)
#define INT_7XX_McBSP1RX (12 + IH2_BASE)
#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
#define INT_7XX_MCSI (16 + IH2_BASE)
#define INT_7XX_uWireTX (17 + IH2_BASE)
#define INT_7XX_uWireRX (18 + IH2_BASE)
#define INT_7XX_SMC_CD (19 + IH2_BASE)
#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
#define INT_7XX_TIMER32K (22 + IH2_BASE)
#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
#define INT_7XX_UPLD (24 + IH2_BASE)
#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
#define INT_7XX_USB_GENI (29 + IH2_BASE)
#define INT_7XX_USB_OTG (30 + IH2_BASE)
#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
#define INT_7XX_RNG (32 + IH2_BASE)
#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
#define INT_7XX_MPUIO (39 + IH2_BASE)
#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
#define INT_7XX_NAND (63 + IH2_BASE)
#define INT_24XX_SYS_NIRQ 7
#define INT_24XX_SDMA_IRQ0 12
......
arch/arm/plat-omap/include/mach/mcbsp.h
View file @ a2bb28a0
......@@ -30,8 +30,8 @@
#include <mach/hardware.h>
#include <mach/clock.h>
#define OMAP730_MCBSP1_BASE 0xfffb1000
#define OMAP730_MCBSP2_BASE 0xfffb1800
#define OMAP7XX_MCBSP1_BASE 0xfffb1000
#define OMAP7XX_MCBSP2_BASE 0xfffb1800
#define OMAP1510_MCBSP1_BASE 0xe1011800
#define OMAP1510_MCBSP2_BASE 0xfffb1000
......@@ -58,7 +58,7 @@
#define OMAP44XX_MCBSP3_BASE 0x49026000
#define OMAP44XX_MCBSP4_BASE 0x48074000
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
#define OMAP_MCBSP_REG_DRR2 0x00
#define OMAP_MCBSP_REG_DRR1 0x02
......
arch/arm/plat-omap/include/mach/mux.h
View file @ a2bb28a0
......@@ -51,23 +51,13 @@
.pu_pd_reg = PU_PD_SEL_##reg, \
.pu_pd_val = status,
#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
.mux_reg = OMAP730_IO_CONF_##reg, \
#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
.mux_reg = OMAP7XX_IO_CONF_##reg, \
.mask_offset = mode_offset, \
.mask = mode,
#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
.pull_reg = OMAP730_IO_CONF_##reg, \
.pull_bit = bit, \
.pull_val = status,
#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
.mux_reg = OMAP850_IO_CONF_##reg, \
.mask_offset = mode_offset, \
.mask = mode,
#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
.pull_reg = OMAP850_IO_CONF_##reg, \
#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
.pull_reg = OMAP7XX_IO_CONF_##reg, \
.pull_bit = bit, \
.pull_val = status,
......@@ -84,21 +74,12 @@
#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
.pu_pd_val = status,
#define MUX_REG_730(reg, mode_offset, mode) \
.mux_reg = OMAP730_IO_CONF_##reg, \
#define MUX_REG_7XX(reg, mode_offset, mode) \
.mux_reg = OMAP7XX_IO_CONF_##reg, \
.mask_offset = mode_offset, \
.mask = mode,
#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
.pull_bit = bit, \
.pull_val = status,
#define MUX_REG_850(reg, mode_offset, mode) \
.mux_reg = OMAP850_IO_CONF_##reg, \
.mask_offset = mode_offset, \
.mask = mode,
#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
.pull_bit = bit, \
.pull_val = status,
......@@ -118,32 +99,21 @@
/*
* OMAP730/850 has a slightly different config for the pin mux.
* - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
* - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
* not the FUNC_MUX_CTRL_x regs from hardware.h
* - for pull-up/down, only has one enable bit which is is in the same register
* as mux config
*/
#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
pull_bit, pull_status, debug_status)\
{ \
.name = desc, \
.debug = debug_status, \
MUX_REG_730(mux_reg, mode_offset, mode) \
PULL_REG_730(mux_reg, pull_bit, pull_status) \
MUX_REG_7XX(mux_reg, mode_offset, mode) \
PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
PU_PD_REG(NA, 0) \
},
#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
pull_bit, pull_status, debug_status)\
{ \
.name = desc, \
.debug = debug_status, \
MUX_REG_850(mux_reg, mode_offset, mode) \
PULL_REG_850(mux_reg, pull_bit, pull_status) \
PU_PD_REG(NA, 0) \
},
#define MUX_CFG_24XX(desc, reg_offset, mode, \
pull_en, pull_mode, dbg) \
{ \
......@@ -232,45 +202,25 @@ struct pin_config {
};
enum omap730_index {
enum omap7xx_index {
/* OMAP 730 keyboard */
E2_730_KBR0,
J7_730_KBR1,
E1_730_KBR2,
F3_730_KBR3,
D2_730_KBR4,
C2_730_KBC0,
D3_730_KBC1,
E4_730_KBC2,
F4_730_KBC3,
E3_730_KBC4,
/* USB */
AA17_730_USB_DM,
W16_730_USB_PU_EN,
W17_730_USB_VBUSI,
};
enum omap850_index {
/* OMAP 850 keyboard */
E2_850_KBR0,
J7_850_KBR1,
E1_850_KBR2,
F3_850_KBR3,
D2_850_KBR4,
C2_850_KBC0,
D3_850_KBC1,
E4_850_KBC2,
F4_850_KBC3,
E3_850_KBC4,
E2_7XX_KBR0,
J7_7XX_KBR1,
E1_7XX_KBR2,
F3_7XX_KBR3,
D2_7XX_KBR4,
C2_7XX_KBC0,
D3_7XX_KBC1,
E4_7XX_KBC2,
F4_7XX_KBC3,
E3_7XX_KBC4,
/* USB */
AA17_850_USB_DM,
W16_850_USB_PU_EN,
W17_850_USB_VBUSI,
AA17_7XX_USB_DM,
W16_7XX_USB_PU_EN,
W17_7XX_USB_VBUSI,
};
enum omap1xxx_index {
/* UART1 (BT_UART_GATING)*/
UART1_TX = 0,
......
arch/arm/plat-omap/include/mach/omap7xx.h 0 → 100644
View file @ a2bb28a0
/* arch/arm/plat-omap/include/mach/omap7xx.h
*
* Hardware definitions for TI OMAP7XX processor.
*
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
* Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
* Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP7XX_H
#define __ASM_ARCH_OMAP7XX_H
/*
* ----------------------------------------------------------------------------
* Base addresses
* ----------------------------------------------------------------------------
*/
/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
#define OMAP7XX_DSP_BASE 0xE0000000
#define OMAP7XX_DSP_SIZE 0x50000
#define OMAP7XX_DSP_START 0xE0000000
#define OMAP7XX_DSPREG_BASE 0xE1000000
#define OMAP7XX_DSPREG_SIZE SZ_128K
#define OMAP7XX_DSPREG_START 0xE1000000
/*
* ----------------------------------------------------------------------------
* OMAP7XX specific configuration registers
* ----------------------------------------------------------------------------
*/
#define OMAP7XX_CONFIG_BASE 0xfffe1000
#define OMAP7XX_IO_CONF_0 0xfffe1070
#define OMAP7XX_IO_CONF_1 0xfffe1074
#define OMAP7XX_IO_CONF_2 0xfffe1078
#define OMAP7XX_IO_CONF_3 0xfffe107c
#define OMAP7XX_IO_CONF_4 0xfffe1080
#define OMAP7XX_IO_CONF_5 0xfffe1084
#define OMAP7XX_IO_CONF_6 0xfffe1088
#define OMAP7XX_IO_CONF_7 0xfffe108c
#define OMAP7XX_IO_CONF_8 0xfffe1090
#define OMAP7XX_IO_CONF_9 0xfffe1094
#define OMAP7XX_IO_CONF_10 0xfffe1098
#define OMAP7XX_IO_CONF_11 0xfffe109c
#define OMAP7XX_IO_CONF_12 0xfffe10a0
#define OMAP7XX_IO_CONF_13 0xfffe10a4
#define OMAP7XX_MODE_1 0xfffe1010
#define OMAP7XX_MODE_2 0xfffe1014
/* CSMI specials: in terms of base + offset */
#define OMAP7XX_MODE2_OFFSET 0x14
/*
* ----------------------------------------------------------------------------
* OMAP7XX traffic controller configuration registers
* ----------------------------------------------------------------------------
*/
#define OMAP7XX_FLASH_CFG_0 0xfffecc10
#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
#define OMAP7XX_FLASH_CFG_1 0xfffecc14
#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
/*
* ----------------------------------------------------------------------------
* OMAP7XX DSP control registers
* ----------------------------------------------------------------------------
*/
#define OMAP7XX_ICR_BASE 0xfffbb800
#define OMAP7XX_DSP_M_CTL 0xfffbb804
#define OMAP7XX_DSP_MMU_BASE 0xfffed200
/*
* ----------------------------------------------------------------------------
* OMAP7XX PCC_UPLD configuration registers
* ----------------------------------------------------------------------------
*/
#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
#endif /* __ASM_ARCH_OMAP7XX_H */
arch/arm/plat-omap/include/mach/uncompress.h
View file @ a2bb28a0
......@@ -25,6 +25,7 @@ unsigned int system_rev;
#define UART_OMAP_MDR1 0x08 /* mode definition register */
#define OMAP_ID_730 0x355F
#define OMAP_ID_850 0x362C
#define ID_MASK 0x7fff
#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
......@@ -53,7 +54,7 @@ static void putc(int c)
/* MMU is not on, so cpu_is_omapXXXX() won't work here */
unsigned int omap_id = omap_get_id();
if (omap_id == OMAP_ID_730)
if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
shift = 0;
if (check_port(uart, shift))
......
arch/arm/plat-omap/io.c
View file @ a2bb28a0
......@@ -13,7 +13,7 @@
#include <linux/io.h>
#include <linux/mm.h>
#include <mach/omap730.h>
#include <mach/omap7xx.h>
#include <mach/omap1510.h>
#include <mach/omap16xx.h>
#include <mach/omap24xx.h>
......@@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
}
if (cpu_is_omap730()) {
if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
if (cpu_is_omap7xx()) {
if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
return XLATE(p, OMAP730_DSPREG_BASE,
OMAP730_DSPREG_START);
if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
return XLATE(p, OMAP7XX_DSPREG_BASE,
OMAP7XX_DSPREG_START);
}
if (cpu_is_omap15xx()) {
if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
......
arch/arm/plat-omap/usb.c
View file @ a2bb28a0
......@@ -614,8 +614,8 @@ omap_otg_init(struct omap_usb_config *config)
if (config->otg || config->register_host) {
syscon &= ~HST_IDLE_EN;
ohci_device.dev.platform_data = config;
if (cpu_is_omap730())
ohci_resources[1].start = INT_730_USB_HHC_1;
if (cpu_is_omap7xx())
ohci_resources[1].start = INT_7XX_USB_HHC_1;
status = platform_device_register(&ohci_device);
if (status)
pr_debug("can't register OHCI device, %d\n", status);
......@@ -626,8 +626,8 @@ omap_otg_init(struct omap_usb_config *config)
if (config->otg) {
syscon &= ~OTG_IDLE_EN;
otg_device.dev.platform_data = config;
if (cpu_is_omap730())
otg_resources[1].start = INT_730_USB_OTG;
if (cpu_is_omap7xx())
otg_resources[1].start = INT_7XX_USB_OTG;
status = platform_device_register(&otg_device);
if (status)
pr_debug("can't register OTG device, %d\n", status);
......@@ -731,7 +731,7 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
void __init omap_usb_init(struct omap_usb_config *pdata)
{
if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx())
if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
omap_otg_init(pdata);
else if (cpu_is_omap15xx())
omap_1510_usb_init(pdata);
......
drivers/spi/omap_uwire.c
View file @ a2bb28a0
......@@ -52,7 +52,7 @@
#include <asm/mach-types.h>
#include <mach/mux.h>
#include <mach/omap730.h> /* OMAP730_IO_CONF registers */
#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
/* FIXME address is now a platform device resource,
......@@ -504,7 +504,7 @@ static int __init uwire_probe(struct platform_device *pdev)
}
clk_enable(uwire->ck);
if (cpu_is_omap730())
if (cpu_is_omap7xx())
uwire_idx_shift = 1;
else
uwire_idx_shift = 2;
......@@ -573,8 +573,8 @@ static int __init omap_uwire_init(void)
}
if (machine_is_omap_perseus2()) {
/* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000;
omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9);
int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
}
return platform_driver_probe(&uwire_driver, uwire_probe);
......
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