Commit a2edaf78 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'imx8mq-4.21' of...

Merge tag 'imx8mq-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late

i.MX8MQ device tree support for 4.21:
 - It contains the initial device tree support for i.MX8MQ - the first
   ARM64 i.MX processor.  It features a quad Cortex-A53 core that
   operates at speeds of up to 1.3 GHz, a Cortex-M4 core for
   low-power processing, a DRAM controller that supports 32-bit/16-bit
   LPDDR4/DDR4/DDR3L memory, and hardware acceleration for 4K video
   playback.
 - A couple of patches from Baruch that add watchdog device for i.MX8MQ
   enable it for imx8mq-evk board.

* tag 'imx8mq-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8mq-evk: enable watchdog
  arm64: dts: imx8mq: add watchdog devices
  MAINTAINERS: add i.MX8 DT path to i.MX architecture
  arm64: add support for i.MX8M EVK board
  arm64: add basic DTS for i.MX8MQ
  arm64: add basic Kconfig symbols for i.MX8
  arm64: dts: ls1046a: add qdma device tree nodes
  arm64: dts: ls1043a: add qdma device tree nodes
  arm64: dts: ls1088a: Add missing dma-ranges property
  arm64: dts: ls1088a: Move fsl-mc node
  arm64: dts: fsl: Add all CPUs in cooling maps
  arm64: dts: Add support for NXP LS1028A SoC
  arm64: dts: layerscape: removed compatible string "snps,dw-pcie"
  arm64: dts: fsl: Add the status property disable PCIe
  arm64: dts: ls1012a: Add FRWY-LS1012A board support
  dt-bindings: Add binding for i.MX8MQ CCM
  arm64: dts: add LX2160AQDS board support
  arm64: dts: add LX2160ARDB board support
  arm64: dts: add QorIQ LX2160A SoC support
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 5e0bd98f 3bbc9abb
* Clock bindings for NXP i.MX8M Quad
Required properties:
- compatible: Should be "fsl,imx8mq-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include the following entries:
- "ckil"
- "osc_25m"
- "osc_27m"
- "clk_ext1"
- "clk_ext2"
- "clk_ext3"
- "clk_ext4"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
for the full list of i.MX8M Quad clock IDs.
...@@ -1523,6 +1523,7 @@ F: arch/arm/mach-imx/ ...@@ -1523,6 +1523,7 @@ F: arch/arm/mach-imx/
F: arch/arm/mach-mxs/ F: arch/arm/mach-mxs/
F: arch/arm/boot/dts/imx* F: arch/arm/boot/dts/imx*
F: arch/arm/configs/imx*_defconfig F: arch/arm/configs/imx*_defconfig
F: arch/arm64/boot/dts/freescale/imx*
F: drivers/clk/imx/ F: drivers/clk/imx/
F: drivers/firmware/imx/ F: drivers/firmware/imx/
F: drivers/soc/imx/ F: drivers/soc/imx/
......
...@@ -142,6 +142,14 @@ config ARCH_MVEBU ...@@ -142,6 +142,14 @@ config ARCH_MVEBU
- Armada 7K SoC Family - Armada 7K SoC Family
- Armada 8K SoC Family - Armada 8K SoC Family
config ARCH_MXC
bool "ARMv8 based NXP i.MX SoC family"
select ARM64_ERRATUM_843419
select ARM64_ERRATUM_845719
help
This enables support for the ARMv8 based SoCs in the
NXP i.MX family.
config ARCH_QCOM config ARCH_QCOM
bool "Qualcomm Platforms" bool "Qualcomm Platforms"
select GPIOLIB select GPIOLIB
......
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
...@@ -13,3 +16,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb ...@@ -13,3 +16,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Freescale LS1012A FRWY Board.
*
* Copyright 2018 NXP
*
* Pramod Kumar <pramod.kumar_1@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls1012a.dtsi"
/ {
model = "LS1012A FRWY Board";
compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
};
&duart0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
...@@ -475,7 +475,7 @@ msi: msi-controller1@1572000 { ...@@ -475,7 +475,7 @@ msi: msi-controller1@1572000 {
}; };
pcie@3400000 { pcie@3400000 {
compatible = "fsl,ls1012a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1012a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -496,6 +496,7 @@ pcie@3400000 { ...@@ -496,6 +496,7 @@ pcie@3400000 {
<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
}; };
......
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NXP LS1028A QDS Board.
*
* Copyright 2018 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
/ {
model = "LS1028A QDS Board";
compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
serial0 = &duart0;
serial1 = &duart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x00000000>;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9847";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
current-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
current-monitor@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x56>;
};
eeprom@57 {
compatible = "atmel,24c512";
reg = <0x57>;
};
};
};
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NXP LS1028A RDB Board.
*
* Copyright 2018 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
/ {
model = "LS1028A RDB Board";
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
serial0 = &duart0;
serial1 = &duart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0000000>;
};
};
&i2c0 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9847";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02>;
current-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
This diff is collapsed.
...@@ -171,8 +171,10 @@ cooling-maps { ...@@ -171,8 +171,10 @@ cooling-maps {
map0 { map0 {
trip = <&cpu_alert>; trip = <&cpu_alert>;
cooling-device = cooling-device =
<&cpu0 THERMAL_NO_LIMIT <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
THERMAL_NO_LIMIT>; <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
...@@ -661,7 +663,7 @@ msi3: msi-controller3@1573000 { ...@@ -661,7 +663,7 @@ msi3: msi-controller3@1573000 {
}; };
pcie@3400000 { pcie@3400000 {
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1043a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -683,10 +685,11 @@ pcie@3400000 { ...@@ -683,10 +685,11 @@ pcie@3400000 {
<0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 2 &gic 0 111 0x4>,
<0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 3 &gic 0 112 0x4>,
<0000 0 0 4 &gic 0 113 0x4>; <0000 0 0 4 &gic 0 113 0x4>;
status = "disabled";
}; };
pcie@3500000 { pcie@3500000 {
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1043a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -708,10 +711,11 @@ pcie@3500000 { ...@@ -708,10 +711,11 @@ pcie@3500000 {
<0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 2 &gic 0 121 0x4>,
<0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 3 &gic 0 122 0x4>,
<0000 0 0 4 &gic 0 123 0x4>; <0000 0 0 4 &gic 0 123 0x4>;
status = "disabled";
}; };
pcie@3600000 { pcie@3600000 {
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1043a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -733,7 +737,30 @@ pcie@3600000 { ...@@ -733,7 +737,30 @@ pcie@3600000 {
<0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 2 &gic 0 155 0x4>,
<0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 3 &gic 0 156 0x4>,
<0000 0 0 4 &gic 0 157 0x4>; <0000 0 0 4 &gic 0 157 0x4>;
status = "disabled";
}; };
qdma: dma-controller@8380000 {
compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qdma-error", "qdma-queue0",
"qdma-queue1", "qdma-queue2", "qdma-queue3";
dma-channels = <8>;
block-number = <1>;
block-offset = <0x10000>;
fsl,dma-queues = <2>;
status-sizes = <64>;
queue-sizes = <64 64>;
big-endian;
};
}; };
firmware { firmware {
......
...@@ -140,8 +140,10 @@ cooling-maps { ...@@ -140,8 +140,10 @@ cooling-maps {
map0 { map0 {
trip = <&cpu_alert>; trip = <&cpu_alert>;
cooling-device = cooling-device =
<&cpu0 THERMAL_NO_LIMIT <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
THERMAL_NO_LIMIT>; <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };
}; };
...@@ -630,7 +632,7 @@ msi3: msi-controller@15a0000 { ...@@ -630,7 +632,7 @@ msi3: msi-controller@15a0000 {
}; };
pcie@3400000 { pcie@3400000 {
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -652,10 +654,11 @@ pcie@3400000 { ...@@ -652,10 +654,11 @@ pcie@3400000 {
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
pcie@3500000 { pcie@3500000 {
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -677,10 +680,11 @@ pcie@3500000 { ...@@ -677,10 +680,11 @@ pcie@3500000 {
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
pcie@3600000 { pcie@3600000 {
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -702,6 +706,28 @@ pcie@3600000 { ...@@ -702,6 +706,28 @@ pcie@3600000 {
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
qdma: dma-controller@8380000 {
compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qdma-error", "qdma-queue0",
"qdma-queue1", "qdma-queue2", "qdma-queue3";
dma-channels = <8>;
block-number = <1>;
block-offset = <0x10000>;
fsl,dma-queues = <2>;
status-sizes = <64>;
queue-sizes = <64 64>;
big-endian;
}; };
}; };
......
...@@ -152,15 +152,14 @@ cooling-maps { ...@@ -152,15 +152,14 @@ cooling-maps {
map0 { map0 {
trip = <&cpu_alert>; trip = <&cpu_alert>;
cooling-device = cooling-device =
<&cpu0 THERMAL_NO_LIMIT <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
THERMAL_NO_LIMIT>; <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
}; <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map1 { <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&cpu_alert>; <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
THERMAL_NO_LIMIT>;
}; };
}; };
}; };
...@@ -174,77 +173,6 @@ timer { ...@@ -174,77 +173,6 @@ timer {
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
}; };
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
msi-parent = <&its>;
#address-cells = <3>;
#size-cells = <1>;
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <1>;
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <2>;
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <3>;
};
dpmac4: dpmac@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <4>;
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <5>;
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <6>;
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <7>;
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <8>;
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <9>;
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
};
};
};
psci { psci {
compatible = "arm,psci-0.2"; compatible = "arm,psci-0.2";
method = "smc"; method = "smc";
...@@ -262,6 +190,7 @@ soc { ...@@ -262,6 +190,7 @@ soc {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
clockgen: clocking@1300000 { clockgen: clocking@1300000 {
compatible = "fsl,ls1088a-clockgen"; compatible = "fsl,ls1088a-clockgen";
...@@ -512,7 +441,7 @@ sec_jr3: jr@40000 { ...@@ -512,7 +441,7 @@ sec_jr3: jr@40000 {
}; };
pcie@3400000 { pcie@3400000 {
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -533,10 +462,11 @@ pcie@3400000 { ...@@ -533,10 +462,11 @@ pcie@3400000 {
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
pcie@3500000 { pcie@3500000 {
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -557,10 +487,11 @@ pcie@3500000 { ...@@ -557,10 +487,11 @@ pcie@3500000 {
<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
pcie@3600000 { pcie@3600000 {
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config"; reg-names = "regs", "config";
...@@ -581,6 +512,7 @@ pcie@3600000 { ...@@ -581,6 +512,7 @@ pcie@3600000 {
<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
cluster1_core0_watchdog: wdt@c000000 { cluster1_core0_watchdog: wdt@c000000 {
...@@ -638,6 +570,77 @@ cluster2_core3_watchdog: wdt@c130000 { ...@@ -638,6 +570,77 @@ cluster2_core3_watchdog: wdt@c130000 {
clocks = <&clockgen 4 3>, <&clockgen 4 3>; clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk"; clock-names = "apb_pclk", "wdog_clk";
}; };
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
msi-parent = <&its>;
#address-cells = <3>;
#size-cells = <1>;
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <1>;
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <2>;
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <3>;
};
dpmac4: dpmac@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <4>;
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <5>;
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <6>;
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <7>;
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <8>;
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <9>;
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
};
};
};
}; };
firmware { firmware {
......
...@@ -119,7 +119,7 @@ CPU_PW20: cpu-pw20 { ...@@ -119,7 +119,7 @@ CPU_PW20: cpu-pw20 {
}; };
&pcie1 { &pcie1 {
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
...@@ -128,7 +128,7 @@ &pcie1 { ...@@ -128,7 +128,7 @@ &pcie1 {
}; };
&pcie2 { &pcie2 {
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
...@@ -137,7 +137,7 @@ &pcie2 { ...@@ -137,7 +137,7 @@ &pcie2 {
}; };
&pcie3 { &pcie3 {
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
...@@ -146,7 +146,7 @@ &pcie3 { ...@@ -146,7 +146,7 @@ &pcie3 {
}; };
&pcie4 { &pcie4 {
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x38 0x00000000 0x0 0x00002000>; /* configuration space */ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
......
...@@ -101,26 +101,14 @@ cooling-maps { ...@@ -101,26 +101,14 @@ cooling-maps {
map0 { map0 {
trip = <&cpu_alert>; trip = <&cpu_alert>;
cooling-device = cooling-device =
<&cpu0 THERMAL_NO_LIMIT <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
THERMAL_NO_LIMIT>; <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
}; <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map1 { <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&cpu_alert>; <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
THERMAL_NO_LIMIT>; <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_alert>;
cooling-device =
<&cpu4 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map3 {
trip = <&cpu_alert>;
cooling-device =
<&cpu6 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
}; };
}; };
}; };
...@@ -630,8 +618,7 @@ qspi: spi@20c0000 { ...@@ -630,8 +618,7 @@ qspi: spi@20c0000 {
}; };
pcie1: pcie@3400000 { pcie1: pcie@3400000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
"snps,dw-pcie";
reg-names = "regs", "config"; reg-names = "regs", "config";
interrupts = <0 108 0x4>; /* Level high type */ interrupts = <0 108 0x4>; /* Level high type */
interrupt-names = "intr"; interrupt-names = "intr";
...@@ -648,11 +635,11 @@ pcie1: pcie@3400000 { ...@@ -648,11 +635,11 @@ pcie1: pcie@3400000 {
<0000 0 0 2 &gic 0 0 0 110 4>, <0000 0 0 2 &gic 0 0 0 110 4>,
<0000 0 0 3 &gic 0 0 0 111 4>, <0000 0 0 3 &gic 0 0 0 111 4>,
<0000 0 0 4 &gic 0 0 0 112 4>; <0000 0 0 4 &gic 0 0 0 112 4>;
status = "disabled";
}; };
pcie2: pcie@3500000 { pcie2: pcie@3500000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
"snps,dw-pcie";
reg-names = "regs", "config"; reg-names = "regs", "config";
interrupts = <0 113 0x4>; /* Level high type */ interrupts = <0 113 0x4>; /* Level high type */
interrupt-names = "intr"; interrupt-names = "intr";
...@@ -669,11 +656,11 @@ pcie2: pcie@3500000 { ...@@ -669,11 +656,11 @@ pcie2: pcie@3500000 {
<0000 0 0 2 &gic 0 0 0 115 4>, <0000 0 0 2 &gic 0 0 0 115 4>,
<0000 0 0 3 &gic 0 0 0 116 4>, <0000 0 0 3 &gic 0 0 0 116 4>,
<0000 0 0 4 &gic 0 0 0 117 4>; <0000 0 0 4 &gic 0 0 0 117 4>;
status = "disabled";
}; };
pcie3: pcie@3600000 { pcie3: pcie@3600000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
"snps,dw-pcie";
reg-names = "regs", "config"; reg-names = "regs", "config";
interrupts = <0 118 0x4>; /* Level high type */ interrupts = <0 118 0x4>; /* Level high type */
interrupt-names = "intr"; interrupt-names = "intr";
...@@ -690,11 +677,11 @@ pcie3: pcie@3600000 { ...@@ -690,11 +677,11 @@ pcie3: pcie@3600000 {
<0000 0 0 2 &gic 0 0 0 120 4>, <0000 0 0 2 &gic 0 0 0 120 4>,
<0000 0 0 3 &gic 0 0 0 121 4>, <0000 0 0 3 &gic 0 0 0 121 4>,
<0000 0 0 4 &gic 0 0 0 122 4>; <0000 0 0 4 &gic 0 0 0 122 4>;
status = "disabled";
}; };
pcie4: pcie@3700000 { pcie4: pcie@3700000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
"snps,dw-pcie";
reg-names = "regs", "config"; reg-names = "regs", "config";
interrupts = <0 123 0x4>; /* Level high type */ interrupts = <0 123 0x4>; /* Level high type */
interrupt-names = "intr"; interrupt-names = "intr";
...@@ -711,6 +698,7 @@ pcie4: pcie@3700000 { ...@@ -711,6 +698,7 @@ pcie4: pcie@3700000 {
<0000 0 0 2 &gic 0 0 0 125 4>, <0000 0 0 2 &gic 0 0 0 125 4>,
<0000 0 0 3 &gic 0 0 0 126 4>, <0000 0 0 3 &gic 0 0 0 126 4>,
<0000 0 0 4 &gic 0 0 0 127 4>; <0000 0 0 4 &gic 0 0 0 127 4>;
status = "disabled";
}; };
sata0: sata@3200000 { sata0: sata@3200000 {
......
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160AQDS
//
// Copyright 2018 NXP
/dts-v1/;
#include "fsl-lx2160a.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS";
compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
aliases {
crypto = &crypto;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "MC34717-3.3VSB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&crypto {
status = "okay";
};
&esdhc0 {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
power-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
power-monitor@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
temperature-sensor@4c {
compatible = "nxp,sa56004";
reg = <0x4c>;
vcc-supply = <&sb_3v3>;
};
temperature-sensor@4d {
compatible = "nxp,sa56004";
reg = <0x4d>;
vcc-supply = <&sb_3v3>;
};
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160ARDB
//
// Copyright 2018 NXP
/dts-v1/;
#include "fsl-lx2160a.dtsi"
/ {
model = "NXP Layerscape LX2160ARDB";
compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
aliases {
crypto = &crypto;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "MC34717-3.3VSB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&crypto {
status = "okay";
};
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
status = "okay";
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "okay";
};
&i2c0 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
power-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
temperature-sensor@4c {
compatible = "nxp,sa56004";
reg = <0x4c>;
vcc-supply = <&sb_3v3>;
};
temperature-sensor@4d {
compatible = "nxp,sa56004";
reg = <0x4d>;
vcc-supply = <&sb_3v3>;
};
};
};
};
&i2c4 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
// IRQ10_B
interrupts = <0 150 0x4>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
This diff is collapsed.
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2017 NXP
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
/dts-v1/;
#include "imx8mq.dtsi"
/ {
model = "NXP i.MX8MQ EVK";
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0xc0000000>;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdog1grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
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