Commit a2fcb84a authored by Robert Richter's avatar Robert Richter Committed by Dan Williams

cxl/port: Remove Component Register base address from struct cxl_port

The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @reg_map instead. Remove the base address.
Signed-off-by: default avatarTerry Bowman <terry.bowman@amd.com>
Signed-off-by: default avatarRobert Richter <rrichter@amd.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20231018171713.1883517-10-rrichter@amd.comSigned-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent f611d98a
...@@ -619,7 +619,6 @@ static int devm_cxl_link_parent_dport(struct device *host, ...@@ -619,7 +619,6 @@ static int devm_cxl_link_parent_dport(struct device *host,
static struct lock_class_key cxl_port_key; static struct lock_class_key cxl_port_key;
static struct cxl_port *cxl_port_alloc(struct device *uport_dev, static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
resource_size_t component_reg_phys,
struct cxl_dport *parent_dport) struct cxl_dport *parent_dport)
{ {
struct cxl_port *port; struct cxl_port *port;
...@@ -670,7 +669,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev, ...@@ -670,7 +669,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
} else } else
dev->parent = uport_dev; dev->parent = uport_dev;
port->component_reg_phys = component_reg_phys;
ida_init(&port->decoder_ida); ida_init(&port->decoder_ida);
port->hdm_end = -1; port->hdm_end = -1;
port->commit_end = -1; port->commit_end = -1;
...@@ -746,7 +744,7 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host, ...@@ -746,7 +744,7 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
struct device *dev; struct device *dev;
int rc; int rc;
port = cxl_port_alloc(uport_dev, component_reg_phys, parent_dport); port = cxl_port_alloc(uport_dev, parent_dport);
if (IS_ERR(port)) if (IS_ERR(port))
return port; return port;
......
...@@ -576,7 +576,6 @@ struct cxl_dax_region { ...@@ -576,7 +576,6 @@ struct cxl_dax_region {
* @nr_dports: number of entries in @dports * @nr_dports: number of entries in @dports
* @hdm_end: track last allocated HDM decoder instance for allocation ordering * @hdm_end: track last allocated HDM decoder instance for allocation ordering
* @commit_end: cursor to track highest committed decoder for commit ordering * @commit_end: cursor to track highest committed decoder for commit ordering
* @component_reg_phys: component register capability base address (optional)
* @dead: last ep has been removed, force port re-creation * @dead: last ep has been removed, force port re-creation
* @depth: How deep this port is relative to the root. depth 0 is the root. * @depth: How deep this port is relative to the root. depth 0 is the root.
* @cdat: Cached CDAT data * @cdat: Cached CDAT data
...@@ -596,7 +595,6 @@ struct cxl_port { ...@@ -596,7 +595,6 @@ struct cxl_port {
int nr_dports; int nr_dports;
int hdm_end; int hdm_end;
int commit_end; int commit_end;
resource_size_t component_reg_phys;
bool dead; bool dead;
unsigned int depth; unsigned int depth;
struct cxl_cdat { struct cxl_cdat {
......
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