Commit a33547cc authored by Andrew Jeffery's avatar Andrew Jeffery Committed by Linus Walleij

pinctrl-aspeed-g5: Never set SCU90[6]

If a pin depending on bit 6 in SCU90 is requested for GPIO, the export
will succeed but changes to the GPIO's value will not be accepted by the
hardware. This is because the pinmux driver has misconfigured the SCU by
writing 1 to the reserved bit.

The description of SCU90[6] from the datasheet is 'Reserved, must keep
at value ”0”'. The fix is to switch pinmux from the bit-flipping macro
to explicitly configuring the .enable and .disable values to zero.

The patch has been tested on an AST2500 EVB.

Fixes: 56e57cb6 (pinctrl: Add pinctrl-aspeed-g5 driver)
Reported-by: default avatarUma Yadlapati <yadlapat@us.ibm.com>
Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent d2cdf5dc
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
#define ASPEED_G5_NR_PINS 228 #define ASPEED_G5_NR_PINS 228
#define COND1 SIG_DESC_BIT(SCU90, 6, 0) #define COND1 { SCU90, BIT(6), 0, 0 }
#define COND2 { SCU94, GENMASK(1, 0), 0, 0 } #define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
#define B14 0 #define B14 0
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment