Commit a361cbc5 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Linus Walleij

pinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pins

This commit normalizes the naming of the Ethernet txclkout pin to be
the same accross Marvell SoCs. It is worth mentioning that the DT
binding documentation of the Armada XP was wrong for MPP12: it said
the function was ge1(txd0), while it is in fact ge1(txclkout). It is
however not really a fix worth sending to stable since it does not
change the behavior, and the driver itself was correct.

Since only the subnames are changed, DT backward compatibility is not
affected.
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent f32f01e1
......@@ -18,7 +18,7 @@ mpp1 1 gpo, uart0(txd)
mpp2 2 gpio, i2c0(sck), uart0(txd)
mpp3 3 gpio, i2c0(sda), uart0(rxd)
mpp4 4 gpio, cpu_pd(vdd)
mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk)
mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk)
mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
......
......@@ -18,7 +18,7 @@ only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, ge0(txclko), lcd(d0)
mpp0 0 gpio, ge0(txclkout), lcd(d0)
mpp1 1 gpio, ge0(txd0), lcd(d1)
mpp2 2 gpio, ge0(txd1), lcd(d2)
mpp3 3 gpio, ge0(txd2), lcd(d3)
......@@ -30,7 +30,7 @@ mpp8 8 gpio, ge0(rxd2), lcd(d8)
mpp9 9 gpio, ge0(rxd3), lcd(d9)
mpp10 10 gpio, ge0(rxctl), lcd(d10)
mpp11 11 gpio, ge0(rxclk), lcd(d11)
mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12)
mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
......
......@@ -55,7 +55,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
MPP_MODE(5,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txclko"),
MPP_FUNCTION(0x1, "ge0", "txclkout"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x4, "spi1", "clk"),
MPP_FUNCTION(0x5, "audio", "mclk")),
......
......@@ -54,7 +54,7 @@ enum armada_xp_variant {
static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txclko", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txclkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
MPP_MODE(1,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
......@@ -103,7 +103,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_MODE(12,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "clkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txclkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)),
MPP_MODE(13,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
......
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