Commit a3bb8a70 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd

dt-bindings: clock: qcom,videocc: add mmcx power domain

On sm8250 videocc requires MMCX power domain to be powered up before
clock controller's registers become available. For now sm8250 was using
external regulator driven by the power domain to describe this
relationship. Switch into specifying power-domain and required opp-state
directly.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210829154757.784699-3-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 730d688f
...@@ -49,6 +49,16 @@ properties: ...@@ -49,6 +49,16 @@ properties:
reg: reg:
maxItems: 1 maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required: required:
- compatible - compatible
- reg - reg
...@@ -63,6 +73,7 @@ additionalProperties: false ...@@ -63,6 +73,7 @@ additionalProperties: false
examples: examples:
- | - |
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@ab00000 { clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc"; compatible = "qcom,sdm845-videocc";
reg = <0x0ab00000 0x10000>; reg = <0x0ab00000 0x10000>;
...@@ -71,5 +82,7 @@ examples: ...@@ -71,5 +82,7 @@ examples:
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
power-domains = <&rpmhpd SM8250_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
}; };
... ...
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