Commit a4f5f398 authored by Mayuresh Chitale's avatar Mayuresh Chitale Committed by Anup Patel

dt-bindings: riscv: Add smstateen entry

Add an entry for the Smstateen extension to the riscv,isa-extensions
property.
Signed-off-by: default avatarMayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 9dbaf381
...@@ -128,6 +128,12 @@ properties: ...@@ -128,6 +128,12 @@ properties:
changes to interrupts as frozen at commit ccbddab ("Merge pull changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia. request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
- const: smstateen
description: |
The standard Smstateen extension for controlling access to CSRs
added by other RISC-V extensions in H/S/VS/U/VU modes and as
ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
- const: ssaia - const: ssaia
description: | description: |
The standard Ssaia supervisor-level extension for the advanced The standard Ssaia supervisor-level extension for the advanced
......
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