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Commit a50e431b authored by Rob Herring's avatar Rob Herring
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dt-bindings: media: mediatek,vcodec: Fix addressing cell sizes 

'dma-ranges' in the example is written for cell sizes of 2 cells, but
the schema and example specify sizes of 1 cell. As the h/w has a bus
address of >32-bits, cell sizes of 2 is correct. Update the schema's
'#address-cells' and '#size-cells' to be 2 and adjust the example
throughout.

There's no error currently because dtc only checks 'dma-ranges' is a
correct multiple number of cells (3) and the schema checking is based on
bracketing of entries.
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220301233501.2110047-1-robh@kernel.org
parent 09a2fb41
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Showing with 64 additions and 58 deletions
Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
View file @ a50e431b
...@@ -72,10 +72,10 @@ properties: ...@@ -72,10 +72,10 @@ properties:
Describes the physical address space of IOMMU maps to memory. Describes the physical address space of IOMMU maps to memory.
"#address-cells": "#address-cells":
const: 1 const: 2
"#size-cells": "#size-cells":
const: 1 const: 2
ranges: true ranges: true
...@@ -205,61 +205,67 @@ examples: ...@@ -205,61 +205,67 @@ examples:
#include <dt-bindings/clock/mt8192-clk.h> #include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/power/mt8192-power.h> #include <dt-bindings/power/mt8192-power.h>
video-codec@16000000 { bus@16000000 {
compatible = "mediatek,mt8192-vcodec-dec"; #address-cells = <2>;
mediatek,scp = <&scp>; #size-cells = <2>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; ranges = <0 0x16000000 0x16000000 0 0x40000>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <1>; video-codec@16000000 {
#size-cells = <1>; compatible = "mediatek,mt8192-vcodec-dec";
ranges = <0 0x16000000 0x40000>; mediatek,scp = <&scp>;
reg = <0x16000000 0x1000>; /* VDEC_SYS */ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
vcodec-lat@10000 { dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
compatible = "mediatek,mtk-vcodec-lat"; #address-cells = <2>;
reg = <0x10000 0x800>; #size-cells = <2>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; ranges = <0 0 0 0x16000000 0 0x40000>;
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, vcodec-lat@10000 {
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, compatible = "mediatek,mtk-vcodec-lat";
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, reg = <0 0x10000 0 0x800>;
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
clocks = <&topckgen CLK_TOP_VDEC_SEL>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
<&vdecsys_soc CLK_VDEC_SOC_VDEC>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
<&topckgen CLK_TOP_MAINPLL_D4>; <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; clocks = <&topckgen CLK_TOP_VDEC_SEL>,
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; <&vdecsys_soc CLK_VDEC_SOC_LAT>,
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
}; <&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
vcodec-core@25000 { assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
compatible = "mediatek,mtk-vcodec-core"; assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
reg = <0x25000 0x1000>; power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>; };
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, vcodec-core@25000 {
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, compatible = "mediatek,mtk-vcodec-core";
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, reg = <0 0x25000 0 0x1000>;
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
clocks = <&topckgen CLK_TOP_VDEC_SEL>, <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
<&vdecsys CLK_VDEC_VDEC>, <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
<&vdecsys CLK_VDEC_LAT>, <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
<&vdecsys CLK_VDEC_LARB1>, <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
<&topckgen CLK_TOP_MAINPLL_D4>; <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; clocks = <&topckgen CLK_TOP_VDEC_SEL>,
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; <&vdecsys CLK_VDEC_VDEC>,
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; <&vdecsys CLK_VDEC_LAT>,
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; <&vdecsys CLK_VDEC_LARB1>,
<&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
};
}; };
}; };
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