Commit a53d26eb authored by Bert Kenward's avatar Bert Kenward Committed by David S. Miller

sfc: tx ring can only have 2048 entries for all EF10 NICs

Fixes: dd248f1b ("sfc: Add PCI ID for Solarflare 8000 series 10/40G NIC")
Reported-by: default avatarPatrick Talbert <ptalbert@redhat.com>
Signed-off-by: default avatarBert Kenward <bkenward@solarflare.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f6478218
...@@ -74,7 +74,10 @@ void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue); ...@@ -74,7 +74,10 @@ void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue);
#define EFX_RXQ_MIN_ENT 128U #define EFX_RXQ_MIN_ENT 128U
#define EFX_TXQ_MIN_ENT(efx) (2 * efx_tx_max_skb_descs(efx)) #define EFX_TXQ_MIN_ENT(efx) (2 * efx_tx_max_skb_descs(efx))
#define EFX_TXQ_MAX_ENT(efx) (EFX_WORKAROUND_35388(efx) ? \ /* All EF10 architecture NICs steal one bit of the DMAQ size for various
* other purposes when counting TxQ entries, so we halve the queue size.
*/
#define EFX_TXQ_MAX_ENT(efx) (EFX_WORKAROUND_EF10(efx) ? \
EFX_MAX_DMAQ_SIZE / 2 : EFX_MAX_DMAQ_SIZE) EFX_MAX_DMAQ_SIZE / 2 : EFX_MAX_DMAQ_SIZE)
static inline bool efx_rss_enabled(struct efx_nic *efx) static inline bool efx_rss_enabled(struct efx_nic *efx)
......
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
*/ */
#define EFX_WORKAROUND_SIENA(efx) (efx_nic_rev(efx) == EFX_REV_SIENA_A0) #define EFX_WORKAROUND_SIENA(efx) (efx_nic_rev(efx) == EFX_REV_SIENA_A0)
#define EFX_WORKAROUND_EF10(efx) (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
#define EFX_WORKAROUND_10G(efx) 1 #define EFX_WORKAROUND_10G(efx) 1
/* Bit-bashed I2C reads cause performance drop */ /* Bit-bashed I2C reads cause performance drop */
......
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