Commit a5ce8523 authored by 周琰杰 (Zhou Yanjie)'s avatar 周琰杰 (Zhou Yanjie) Committed by Thomas Bogendoerfer

MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.

1.Fix bugs when detecting ways value of JZ4775's L2 cache.
2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.
Signed-off-by: default avatar周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent a9fee3a5
...@@ -228,6 +228,7 @@ static inline int __init mips_sc_probe(void) ...@@ -228,6 +228,7 @@ static inline int __init mips_sc_probe(void)
* contradicted by all documentation. * contradicted by all documentation.
*/ */
case MACH_INGENIC_JZ4770: case MACH_INGENIC_JZ4770:
case MACH_INGENIC_JZ4775:
c->scache.ways = 4; c->scache.ways = 4;
break; break;
...@@ -236,6 +237,7 @@ static inline int __init mips_sc_probe(void) ...@@ -236,6 +237,7 @@ static inline int __init mips_sc_probe(void)
* but that is contradicted by all documentation. * but that is contradicted by all documentation.
*/ */
case MACH_INGENIC_X1000: case MACH_INGENIC_X1000:
case MACH_INGENIC_X1000E:
c->scache.sets = 256; c->scache.sets = 256;
c->scache.ways = 4; c->scache.ways = 4;
break; break;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment