Commit a5e0c15d authored by Leela Krishna Amudala's avatar Leela Krishna Amudala Committed by Kukjin Kim

ARM: EXYNOS: Add bus clock for FIMD

This patch adds the bus clock for FIMD and changes the device name
for lcd clock
Signed-off-by: default avatarLeela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: default avatarJingoo Han <jg1.han@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent a8321393
...@@ -891,6 +891,13 @@ static struct clk exynos5_clk_mdma1 = { ...@@ -891,6 +891,13 @@ static struct clk exynos5_clk_mdma1 = {
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}; };
static struct clk exynos5_clk_fimd1 = {
.name = "fimd",
.devname = "exynos5-fb.1",
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 0),
};
struct clk *exynos5_clkset_group_list[] = { struct clk *exynos5_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux, [0] = &clk_ext_xtal_mux,
[1] = NULL, [1] = NULL,
...@@ -1120,6 +1127,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = { ...@@ -1120,6 +1127,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
}; };
struct clksrc_clk exynos5_clk_sclk_fimd1 = {
.clk = {
.name = "sclk_fimd",
.devname = "exynos5-fb.1",
.enable = exynos5_clksrc_mask_disp1_0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos5_clksrcs[] = { static struct clksrc_clk exynos5_clksrcs[] = {
{ {
.clk = { .clk = {
...@@ -1129,16 +1148,6 @@ static struct clksrc_clk exynos5_clksrcs[] = { ...@@ -1129,16 +1148,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 }, .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
}, {
.clk = {
.name = "sclk_fimd",
.devname = "s3cfb.1",
.enable = exynos5_clksrc_mask_disp1_0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
}, { }, {
.clk = { .clk = {
.name = "aclk_266_gscl", .name = "aclk_266_gscl",
...@@ -1240,12 +1249,14 @@ static struct clksrc_clk *exynos5_sysclks[] = { ...@@ -1240,12 +1249,14 @@ static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mdout_spi0, &exynos5_clk_mdout_spi0,
&exynos5_clk_mdout_spi1, &exynos5_clk_mdout_spi1,
&exynos5_clk_mdout_spi2, &exynos5_clk_mdout_spi2,
&exynos5_clk_sclk_fimd1,
}; };
static struct clk *exynos5_clk_cdev[] = { static struct clk *exynos5_clk_cdev[] = {
&exynos5_clk_pdma0, &exynos5_clk_pdma0,
&exynos5_clk_pdma1, &exynos5_clk_pdma1,
&exynos5_clk_mdma1, &exynos5_clk_mdma1,
&exynos5_clk_fimd1,
}; };
static struct clksrc_clk *exynos5_clksrc_cdev[] = { static struct clksrc_clk *exynos5_clksrc_cdev[] = {
...@@ -1274,6 +1285,7 @@ static struct clk_lookup exynos5_clk_lookup[] = { ...@@ -1274,6 +1285,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
}; };
static unsigned long exynos5_epll_get_rate(struct clk *clk) static unsigned long exynos5_epll_get_rate(struct clk *clk)
......
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