Commit a64021e8 authored by Horia Geant?'s avatar Horia Geant? Committed by Greg Kroah-Hartman

crypto: caam - make write transactions bufferable on PPC platforms

commit e7a7104e upstream.

Previous change (see "Fixes" tag) to the MCFGR register
clears AWCACHE[0] ("bufferable" AXI3 attribute) (which is "1" at POR).

This makes all writes non-bufferable, causing a ~ 5% performance drop
for PPC-based platforms.

Rework previous change such that MCFGR[AWCACHE]=4'b0011
(bufferable + cacheable) for all platforms.
Note: For ARM-based platforms, AWCACHE[0] is ignored
by the interconnect IP.

Fixes: f1096749 ("crypto: caam - fix snooping for write transactions")
Signed-off-by: default avatarHoria Geant? <horia.geanta@nxp.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4bbf076a
...@@ -534,8 +534,8 @@ static int caam_probe(struct platform_device *pdev) ...@@ -534,8 +534,8 @@ static int caam_probe(struct platform_device *pdev)
* long pointers in master configuration register * long pointers in master configuration register
*/ */
clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH | clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE |
MCFGR_LONG_PTR : 0)); (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
/* /*
* Read the Compile Time paramters and SCFGR to determine * Read the Compile Time paramters and SCFGR to determine
......
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