Commit a75dcbf4 authored by Dong Aisheng's avatar Dong Aisheng Committed by Ulf Hansson

mmc: sdhci-esdhc-imx: clear tuning bits during driver probe

The tuning bits like FBCLK_SEL, SMP_CLK_SEL and DLY_CELL which affects
timing may have already been set by ROM if booting from SD3.0 mode like
SDR104. Let's clear it first during driver probe before doing the new
card enumeration to avoid working on the wrong timing.

Note that tuning bits are dynamical settings which may need to be kept
during MMC_PM_KEEP_POWER suspend, so we did not put them into hwinit
function.
Signed-off-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 19dbfdd3
...@@ -1224,6 +1224,11 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) ...@@ -1224,6 +1224,11 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
host->mmc->caps |= MMC_CAP_1_8V_DDR; host->mmc->caps |= MMC_CAP_1_8V_DDR;
if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
/* clear tuning bits in case ROM has set it already */
writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR);
writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
} }
if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment