Commit a7ef1ead authored by Kevin Cernekee's avatar Kevin Cernekee Committed by Ralf Baechle

MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizes

CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c.  However,
it is currently hardwired to use an L1_SHIFT of 6 (64 bytes).  Move the
L1_SHIFT selection into the CPU or SoC section so that other SoCs can
select different values.
Signed-off-by: default avatarKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8162/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3677a283
...@@ -327,6 +327,7 @@ config MIPS_MALTA ...@@ -327,6 +327,7 @@ config MIPS_MALTA
select I8259 select I8259
select MIPS_BONITO64 select MIPS_BONITO64
select MIPS_CPU_SCACHE select MIPS_CPU_SCACHE
select MIPS_L1_CACHE_SHIFT_6
select PCI_GT64XXX_PCI0 select PCI_GT64XXX_PCI0
select MIPS_MSC select MIPS_MSC
select SWAP_IO_SPACE select SWAP_IO_SPACE
...@@ -1908,7 +1909,6 @@ config IP22_CPU_SCACHE ...@@ -1908,7 +1909,6 @@ config IP22_CPU_SCACHE
config MIPS_CPU_SCACHE config MIPS_CPU_SCACHE
bool bool
select BOARD_SCACHE select BOARD_SCACHE
select MIPS_L1_CACHE_SHIFT_6
config R5000_CPU_SCACHE config R5000_CPU_SCACHE
bool bool
......
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