Commit a83fdfae authored by Stephen Boyd's avatar Stephen Boyd

Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and...

Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and 'clk-ti-flag-fix' into clk-next

* clk-davinci:
  clk: davinci: Remove redundant dev_err calls
  clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
  clk: davinci: New driver for TI DA8XX CFGCHIP clocks
  dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks
  clk: davinci: Add platform information for TI DM646x PSC
  clk: davinci: Add platform information for TI DM644x PSC
  clk: davinci: Add platform information for TI DM365 PSC
  clk: davinci: Add platform information for TI DM355 PSC
  clk: davinci: Add platform information for TI DA850 PSC
  clk: davinci: Add platform information for TI DA830 PSC
  clk: davinci: New driver for davinci PSC clocks
  dt-bindings: clock: New bindings for TI Davinci PSC
  clk: davinci: Add platform information for TI DM646x PLL
  clk: davinci: Add platform information for TI DM644x PLL
  clk: davinci: Add platform information for TI DM365 PLL
  clk: davinci: Add platform information for TI DM355 PLL
  clk: davinci: Add platform information for TI DA850 PLL
  clk: davinci: Add platform information for TI DA830 PLL
  clk: davinci: New driver for davinci PLL clocks
  dt-bindings: clock: Add new bindings for TI Davinci PLL clocks

* clk-si544:
  clk: Add driver for the si544 clock generator chip

* clk-rockchip:
  clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
  clk: rockchip: Fix error return in phase clock registration
  clk: rockchip: Correct the behaviour of restoring cached phase
  clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
  clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
  clk: rockchip: Add 1.6GHz PLL rate for rk3399
  clk: rockchip: Restore the clock phase after the rate was changed
  clk: rockchip: Prevent calculating mmc phase if clock rate is zero
  clk: rockchip: Free the memory on the error path
  clk: rockchip: document hdmi_phy external input for rk3328
  clk: rockchip: add flags for rk3328 dclk_lcdc
  clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks
  clk: rockchip: protect all remaining rk3328 interconnect clocks
  clk: rockchip: export sclk_hdmi_sfc on rk3328
  clk: rockchip: remove HCLK_VIO from rk3328 dt header
  clk: rockchip: fix hclk_vio_niu on rk3328

* clk-uniphier:
  clk: uniphier: add additional ethernet clock lines for Pro4
  clk: uniphier: add SATA clock control support
  clk: uniphier: add PCIe clock control support
  clk: uniphier: add ethernet clock control support for PXs3
  clk: uniphier: add Pro4/Pro5/PXs2 audio system clock

* clk-ti-flag-fix:
  clk: ti: fix flag space conflict with clkctrl clocks
  clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
......@@ -32,6 +32,7 @@ clock-output-names:
- "clkin_i2s" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
- "phy_50m_out" - output clock of the pll in the mac phy
- "hdmi_phy" - output clock of the hdmi phy pll - optional
Example: Clock controller node:
......
Binding for Silicon Labs 544 programmable I2C clock generator.
Reference
This binding uses the common clock binding[1]. Details about the device can be
found in the datasheet[2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si544 datasheet
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
Required properties:
- compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
to the speed grade of the chip.
- reg: I2C device address.
- #clock-cells: From common clock bindings: Shall be 0.
Optional properties:
- clock-output-names: From common clock bindings. Recommended to be "si544".
Example:
si544: clock-controller@55 {
reg = <0x55>;
#clock-cells = <0>;
compatible = "silabs,si544b";
};
Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
registers call CFGCHIPn. Some of these registers function as clock
gates. This document describes the bindings for those clocks.
All of the clock nodes described below must be child nodes of a CFGCHIP node
(compatible = "ti,da830-cfgchip").
USB PHY clocks
--------------
Required properties:
- compatible: shall be "ti,da830-usb-phy-clocks".
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "fck", "usb_refclkin", "auxclk"
This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
eHRPWM Time Base Clock (TBCLK)
------------------------------
Required properties:
- compatible: shall be "ti,da830-tbclksync".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandle to the parent clock
- clock-names: shall be "fck"
PLL DIV4.5 divider
------------------
Required properties:
- compatible: shall be "ti,da830-div4p5ena".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandle to the parent clock
- clock-names: shall be "pll0_pllout"
EMIFA clock source (ASYNC1)
---------------------------
Required properties:
- compatible: shall be "ti,da850-async1-clksrc".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "pll0_sysclk3", "div4.5"
ASYNC3 clock source
-------------------
Required properties:
- compatible: shall be "ti,da850-async3-clksrc".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
Examples:
cfgchip: syscon@1417c {
compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
reg = <0x1417c 0x14>;
usb_phy_clk: usb-phy-clocks {
compatible = "ti,da830-usb-phy-clocks";
#clock-cells = <1>;
clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
clock-names = "fck", "usb_refclkin", "auxclk";
};
ehrpwm_tbclk: ehrpwm_tbclk {
compatible = "ti,da830-tbclksync";
#clock-cells = <0>;
clocks = <&psc1 17>;
clock-names = "fck";
};
div4p5_clk: div4.5 {
compatible = "ti,da830-div4p5ena";
#clock-cells = <0>;
clocks = <&pll0_pllout>;
clock-names = "pll0_pllout";
};
async1_clk: async1 {
compatible = "ti,da850-async1-clksrc";
#clock-cells = <0>;
clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
clock-names = "pll0_sysclk3", "div4.5";
};
async3_clk: async3 {
compatible = "ti,da850-async3-clksrc";
#clock-cells = <0>;
clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
clock-names = "pll0_sysclk2", "pll1_sysclk2";
};
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
Binding for TI DaVinci PLL Controllers
The PLL provides clocks to most of the components on the SoC. In addition
to the PLL itself, this controller also contains bypasses, gates, dividers,
an multiplexers for various clock signals.
Required properties:
- compatible: shall be one of:
- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
- reg: physical base address and size of the controller's register area.
- clocks: phandles corresponding to the clock names
- clock-names: names of the clock sources - depends on compatible string
- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
- for "ti,da850-pll1", shall be "clksrc"
Optional properties:
- ti,clkmode-square-wave: Indicates that the the board is supplying a square
wave input on the OSCIN pin instead of using a crystal oscillator.
This property is only valid when compatible = "ti,da850-pll0".
Optional child nodes:
pllout
Describes the main PLL clock output (before POSTDIV). The node name must
be "pllout".
Required properties:
- #clock-cells: shall be 0
sysclk
Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
domains. The node name must be "sysclk". Consumers of this node should
use "n" in "SYSCLKn" as the index parameter for the clock cell.
Required properties:
- #clock-cells: shall be 1
auxclk
Describes the AUXCLK output of the PLL. The node name must be "auxclk".
This child node is only valid when compatible = "ti,da850-pll0".
Required properties:
- #clock-cells: shall be 0
obsclk
Describes the OBSCLK output of the PLL. The node name must be "obsclk".
Required properties:
- #clock-cells: shall be 0
Examples:
pll0: clock-controller@11000 {
compatible = "ti,da850-pll0";
reg = <0x11000 0x1000>;
clocks = <&ref_clk>, <&pll1_sysclk 3>;
clock-names = "clksrc", "extclksrc";
ti,clkmode-square-wave;
pll0_pllout: pllout {
#clock-cells = <0>;
};
pll0_sysclk: sysclk {
#clock-cells = <1>;
};
pll0_auxclk: auxclk {
#clock-cells = <0>;
};
pll0_obsclk: obsclk {
#clock-cells = <0>;
};
};
pll1: clock-controller@21a000 {
compatible = "ti,da850-pll1";
reg = <0x21a000 0x1000>;
clocks = <&ref_clk>;
clock-names = "clksrc";
pll0_sysclk: sysclk {
#clock-cells = <1>;
};
pll0_obsclk: obsclk {
#clock-cells = <0>;
};
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
Binding for TI DaVinci Power Sleep Controller (PSC)
The PSC provides power management, clock gating and reset functionality. It is
primarily used for clocking.
Required properties:
- compatible: shall be one of:
- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
- reg: physical base address and size of the controller's register area
- #clock-cells: from common clock binding; shall be set to 1
- #power-domain-cells: from generic power domain binding; shall be set to 1.
- clocks: phandles to clocks corresponding to the clock-names property
- clock-names: list of parent clock names - depends on compatible value
- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
"pll0_sysclk4", "pll0_sysclk6", "async1"
- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
Optional properties:
- #reset-cells: from reset binding; shall be set to 1 - only applicable when
at least one local domain provides a local reset.
Consumers:
Clock, power domain and reset consumers shall use the local power domain
module ID (LPSC) as the index corresponding to the clock cell. Refer to
the device-specific datasheet to find these numbers. NB: Most local
domains only provide a clock/power domain and not a reset.
Examples:
psc0: clock-controller@10000 {
compatible = "ti,da850-psc0";
reg = <0x10000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
<&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
clock_names = "pll0_sysclk1", "pll0_sysclk2",
"pll0_sysclk4", "pll0_sysclk6", "async1";
};
psc1: clock-controller@227000 {
compatible = "ti,da850-psc1";
reg = <0x227000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
};
/* consumer */
dsp: dsp@11800000 {
compatible = "ti,da850-dsp";
reg = <0x11800000 0x40000>,
<0x11e00000 0x8000>,
<0x11f00000 0x8000>,
<0x01c14044 0x4>,
<0x01c14174 0x8>;
reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
interrupt-parent = <&intc>;
interrupts = <28>;
clocks = <&psc0 15>;
power-domains = <&psc0 15>;
resets = <&psc0 15>;
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- Documentation/devicetree/bindings/power/power_domain.txt
- Documentation/devicetree/bindings/reset/reset.txt
......@@ -13793,6 +13793,13 @@ F: arch/arm/mach-davinci/
F: drivers/i2c/busses/i2c-davinci.c
F: arch/arm/boot/dts/da850*
TI DAVINCI SERIES CLOCK DRIVER
M: David Lechner <david@lechnology.com>
R: Sekhar Nori <nsekhar@ti.com>
S: Maintained
F: Documentation/devicetree/bindings/clock/ti/davinci/
F: drivers/clk/davinci/
TI DAVINCI SERIES GPIO DRIVER
M: Keerthy <j-keerthy@ti.com>
L: linux-gpio@vger.kernel.org
......
......@@ -93,6 +93,15 @@ config COMMON_CLK_SI514
This driver supports the Silicon Labs 514 programmable clock
generator.
config COMMON_CLK_SI544
tristate "Clock driver for SiLabs 544 devices"
depends on I2C
select REGMAP_I2C
help
---help---
This driver supports the Silicon Labs 544 programmable clock
generator.
config COMMON_CLK_SI570
tristate "Clock driver for SiLabs 570 and compatible devices"
depends on I2C
......
......@@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
obj-$(CONFIG_COMMON_CLK_SCPI) += clk-scpi.o
obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o
obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o
obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o
......@@ -62,6 +63,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
obj-$(CONFIG_H8300) += h8300/
obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-y += imgtec/
......
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Silicon Labs Si544 Programmable Oscillator
* Copyright (C) 2018 Topic Embedded Products
* Author: Mike Looijmans <mike.looijmans@topic.nl>
*/
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
/* I2C registers (decimal as in datasheet) */
#define SI544_REG_CONTROL 7
#define SI544_REG_OE_STATE 17
#define SI544_REG_HS_DIV 23
#define SI544_REG_LS_HS_DIV 24
#define SI544_REG_FBDIV0 26
#define SI544_REG_FBDIV8 27
#define SI544_REG_FBDIV16 28
#define SI544_REG_FBDIV24 29
#define SI544_REG_FBDIV32 30
#define SI544_REG_FBDIV40 31
#define SI544_REG_FCAL_OVR 69
#define SI544_REG_ADPLL_DELTA_M0 231
#define SI544_REG_ADPLL_DELTA_M8 232
#define SI544_REG_ADPLL_DELTA_M16 233
#define SI544_REG_PAGE_SELECT 255
/* Register values */
#define SI544_CONTROL_RESET BIT(7)
#define SI544_CONTROL_MS_ICAL2 BIT(3)
#define SI544_OE_STATE_ODC_OE BIT(0)
/* Max freq depends on speed grade */
#define SI544_MIN_FREQ 200000U
/* Si544 Internal oscilator runs at 55.05 MHz */
#define FXO 55050000U
/* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
#define FVCO_MIN 10800000000ULL
#define HS_DIV_MAX 2046
#define HS_DIV_MAX_ODD 33
/* Lowest frequency synthesizeable using only the HS divider */
#define MIN_HSDIV_FREQ (FVCO_MIN / HS_DIV_MAX)
enum si544_speed_grade {
si544a,
si544b,
si544c,
};
struct clk_si544 {
struct clk_hw hw;
struct regmap *regmap;
struct i2c_client *i2c_client;
enum si544_speed_grade speed_grade;
};
#define to_clk_si544(_hw) container_of(_hw, struct clk_si544, hw)
/**
* struct clk_si544_muldiv - Multiplier/divider settings
* @fb_div_frac: integer part of feedback divider (32 bits)
* @fb_div_int: fractional part of feedback divider (11 bits)
* @hs_div: 1st divider, 5..2046, must be even when >33
* @ls_div_bits: 2nd divider, as 2^x, range 0..5
* If ls_div_bits is non-zero, hs_div must be even
*/
struct clk_si544_muldiv {
u32 fb_div_frac;
u16 fb_div_int;
u16 hs_div;
u8 ls_div_bits;
};
/* Enables or disables the output driver */
static int si544_enable_output(struct clk_si544 *data, bool enable)
{
return regmap_update_bits(data->regmap, SI544_REG_OE_STATE,
SI544_OE_STATE_ODC_OE, enable ? SI544_OE_STATE_ODC_OE : 0);
}
/* Retrieve clock multiplier and dividers from hardware */
static int si544_get_muldiv(struct clk_si544 *data,
struct clk_si544_muldiv *settings)
{
int err;
u8 reg[6];
err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2);
if (err)
return err;
settings->ls_div_bits = (reg[1] >> 4) & 0x07;
settings->hs_div = (reg[1] & 0x07) << 8 | reg[0];
err = regmap_bulk_read(data->regmap, SI544_REG_FBDIV0, reg, 6);
if (err)
return err;
settings->fb_div_int = reg[4] | (reg[5] & 0x07) << 8;
settings->fb_div_frac = reg[0] | reg[1] << 8 | reg[2] << 16 |
reg[3] << 24;
return 0;
}
static int si544_set_muldiv(struct clk_si544 *data,
struct clk_si544_muldiv *settings)
{
int err;
u8 reg[6];
reg[0] = settings->hs_div;
reg[1] = settings->hs_div >> 8 | settings->ls_div_bits << 4;
err = regmap_bulk_write(data->regmap, SI544_REG_HS_DIV, reg, 2);
if (err < 0)
return err;
reg[0] = settings->fb_div_frac;
reg[1] = settings->fb_div_frac >> 8;
reg[2] = settings->fb_div_frac >> 16;
reg[3] = settings->fb_div_frac >> 24;
reg[4] = settings->fb_div_int;
reg[5] = settings->fb_div_int >> 8;
/*
* Writing to SI544_REG_FBDIV40 triggers the clock change, so that
* must be written last
*/
return regmap_bulk_write(data->regmap, SI544_REG_FBDIV0, reg, 6);
}
static bool is_valid_frequency(const struct clk_si544 *data,
unsigned long frequency)
{
unsigned long max_freq = 0;
if (frequency < SI544_MIN_FREQ)
return false;
switch (data->speed_grade) {
case si544a:
max_freq = 1500000000;
break;
case si544b:
max_freq = 800000000;
break;
case si544c:
max_freq = 350000000;
break;
}
return frequency <= max_freq;
}
/* Calculate divider settings for a given frequency */
static int si544_calc_muldiv(struct clk_si544_muldiv *settings,
unsigned long frequency)
{
u64 vco;
u32 ls_freq;
u32 tmp;
u8 res;
/* Determine the minimum value of LS_DIV and resulting target freq. */
ls_freq = frequency;
settings->ls_div_bits = 0;
if (frequency >= MIN_HSDIV_FREQ) {
settings->ls_div_bits = 0;
} else {
res = 1;
tmp = 2 * HS_DIV_MAX;
while (tmp <= (HS_DIV_MAX * 32)) {
if (((u64)frequency * tmp) >= FVCO_MIN)
break;
++res;
tmp <<= 1;
}
settings->ls_div_bits = res;
ls_freq = frequency << res;
}
/* Determine minimum HS_DIV by rounding up */
vco = FVCO_MIN + ls_freq - 1;
do_div(vco, ls_freq);
settings->hs_div = vco;
/* round up to even number when required */
if ((settings->hs_div & 1) &&
(settings->hs_div > HS_DIV_MAX_ODD || settings->ls_div_bits))
++settings->hs_div;
/* Calculate VCO frequency (in 10..12GHz range) */
vco = (u64)ls_freq * settings->hs_div;
/* Calculate the integer part of the feedback divider */
tmp = do_div(vco, FXO);
settings->fb_div_int = vco;
/* And the fractional bits using the remainder */
vco = (u64)tmp << 32;
do_div(vco, FXO);
settings->fb_div_frac = vco;
return 0;
}
/* Calculate resulting frequency given the register settings */
static unsigned long si544_calc_rate(struct clk_si544_muldiv *settings)
{
u32 d = settings->hs_div * BIT(settings->ls_div_bits);
u64 vco;
/* Calculate VCO from the fractional part */
vco = (u64)settings->fb_div_frac * FXO;
vco += (FXO / 2);
vco >>= 32;
/* Add the integer part of the VCO frequency */
vco += (u64)settings->fb_div_int * FXO;
/* Apply divider to obtain the generated frequency */
do_div(vco, d);
return vco;
}
static unsigned long si544_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_si544 *data = to_clk_si544(hw);
struct clk_si544_muldiv settings;
int err;
err = si544_get_muldiv(data, &settings);
if (err)
return 0;
return si544_calc_rate(&settings);
}
static long si544_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct clk_si544 *data = to_clk_si544(hw);
struct clk_si544_muldiv settings;
int err;
if (!is_valid_frequency(data, rate))
return -EINVAL;
err = si544_calc_muldiv(&settings, rate);
if (err)
return err;
return si544_calc_rate(&settings);
}
/*
* Update output frequency for "big" frequency changes
*/
static int si544_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_si544 *data = to_clk_si544(hw);
struct clk_si544_muldiv settings;
int err;
if (!is_valid_frequency(data, rate))
return -EINVAL;
err = si544_calc_muldiv(&settings, rate);
if (err)
return err;
si544_enable_output(data, false);
/* Allow FCAL for this frequency update */
err = regmap_write(data->regmap, SI544_REG_FCAL_OVR, 0);
if (err < 0)
return err;
err = si544_set_muldiv(data, &settings);
if (err < 0)
return err; /* Undefined state now, best to leave disabled */
/* Trigger calibration */
err = regmap_write(data->regmap, SI544_REG_CONTROL,
SI544_CONTROL_MS_ICAL2);
if (err < 0)
return err;
/* Applying a new frequency can take up to 10ms */
usleep_range(10000, 12000);
si544_enable_output(data, true);
return err;
}
static const struct clk_ops si544_clk_ops = {
.recalc_rate = si544_recalc_rate,
.round_rate = si544_round_rate,
.set_rate = si544_set_rate,
};
static bool si544_regmap_is_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case SI544_REG_CONTROL:
case SI544_REG_FCAL_OVR:
return true;
default:
return false;
}
}
static const struct regmap_config si544_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.max_register = SI544_REG_PAGE_SELECT,
.volatile_reg = si544_regmap_is_volatile,
};
static int si544_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct clk_si544 *data;
struct clk_init_data init;
int err;
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
init.ops = &si544_clk_ops;
init.flags = 0;
init.num_parents = 0;
data->hw.init = &init;
data->i2c_client = client;
data->speed_grade = id->driver_data;
if (of_property_read_string(client->dev.of_node, "clock-output-names",
&init.name))
init.name = client->dev.of_node->name;
data->regmap = devm_regmap_init_i2c(client, &si544_regmap_config);
if (IS_ERR(data->regmap))
return PTR_ERR(data->regmap);
i2c_set_clientdata(client, data);
/* Select page 0, just to be sure, there appear to be no more */
err = regmap_write(data->regmap, SI544_REG_PAGE_SELECT, 0);
if (err < 0)
return err;
err = devm_clk_hw_register(&client->dev, &data->hw);
if (err) {
dev_err(&client->dev, "clock registration failed\n");
return err;
}
err = devm_of_clk_add_hw_provider(&client->dev, of_clk_hw_simple_get,
&data->hw);
if (err) {
dev_err(&client->dev, "unable to add clk provider\n");
return err;
}
return 0;
}
static const struct i2c_device_id si544_id[] = {
{ "si544a", si544a },
{ "si544b", si544b },
{ "si544c", si544c },
{ }
};
MODULE_DEVICE_TABLE(i2c, si544_id);
static const struct of_device_id clk_si544_of_match[] = {
{ .compatible = "silabs,si544a" },
{ .compatible = "silabs,si544b" },
{ .compatible = "silabs,si544c" },
{ },
};
MODULE_DEVICE_TABLE(of, clk_si544_of_match);
static struct i2c_driver si544_driver = {
.driver = {
.name = "si544",
.of_match_table = clk_si544_of_match,
},
.probe = si544_probe,
.id_table = si544_id,
};
module_i2c_driver(si544_driver);
MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
MODULE_DESCRIPTION("Si544 driver");
MODULE_LICENSE("GPL");
# SPDX-License-Identifier: GPL-2.0
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o
obj-y += pll.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += pll-dm644x.o
obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pll-dm646x.o
obj-y += psc.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += psc-dm355.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += psc-dm365.o
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += psc-dm644x.o
obj-$(CONFIG_ARCH_DAVINCI_DM646x) += psc-dm646x.o
endif
This diff is collapsed.
// SPDX-License-Identifier: GPL-2.0
/*
* PLL clock descriptions for TI DA830/OMAP-L137/AM17XX
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/clkdev.h>
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/types.h>
#include "pll.h"
static const struct davinci_pll_clk_info da830_pll_info = {
.name = "pll0",
.pllm_mask = GENMASK(4, 0),
.pllm_min = 4,
.pllm_max = 32,
.pllout_min_rate = 300000000,
.pllout_max_rate = 600000000,
.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
};
/*
* NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
* meaning that we could change the divider as long as we keep the correct
* ratio between all of the clocks, but we don't support that because there is
* currently not a need for it.
*/
SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
int da830_pll_init(struct device *dev, void __iomem *base)
{
struct clk *clk;
davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base);
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1");
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0");
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0");
clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1");
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1");
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0");
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
clk_register_clkdev(clk, NULL, "i2c_davinci.1");
clk_register_clkdev(clk, "timer0", NULL);
clk_register_clkdev(clk, NULL, "davinci-wdt");
return 0;
}
// SPDX-License-Identifier: GPL-2.0
/*
* PLL clock descriptions for TI DA850/OMAP-L138/AM18XX
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/da8xx-cfgchip.h>
#include <linux/of.h>
#include <linux/types.h>
#include "pll.h"
#define OCSEL_OCSRC_OSCIN 0x14
#define OCSEL_OCSRC_PLL0_SYSCLK(n) (0x16 + (n))
#define OCSEL_OCSRC_PLL1_OBSCLK 0x1e
#define OCSEL_OCSRC_PLL1_SYSCLK(n) (0x16 + (n))
static const struct davinci_pll_clk_info da850_pll0_info = {
.name = "pll0",
.unlock_reg = CFGCHIP(0),
.unlock_mask = CFGCHIP0_PLL_MASTER_LOCK,
.pllm_mask = GENMASK(4, 0),
.pllm_min = 4,
.pllm_max = 32,
.pllout_min_rate = 300000000,
.pllout_max_rate = 600000000,
.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
PLL_HAS_EXTCLKSRC,
};
/*
* NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
* meaning that we could change the divider as long as we keep the correct
* ratio between all of the clocks, but we don't support that because there is
* currently not a need for it.
*/
SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV);
SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV);
SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
static const char * const da850_pll0_obsclk_parent_names[] = {
"oscin",
"pll0_sysclk1",
"pll0_sysclk2",
"pll0_sysclk3",
"pll0_sysclk4",
"pll0_sysclk5",
"pll0_sysclk6",
"pll0_sysclk7",
"pll1_obsclk",
};
static u32 da850_pll0_obsclk_table[] = {
OCSEL_OCSRC_OSCIN,
OCSEL_OCSRC_PLL0_SYSCLK(1),
OCSEL_OCSRC_PLL0_SYSCLK(2),
OCSEL_OCSRC_PLL0_SYSCLK(3),
OCSEL_OCSRC_PLL0_SYSCLK(4),
OCSEL_OCSRC_PLL0_SYSCLK(5),
OCSEL_OCSRC_PLL0_SYSCLK(6),
OCSEL_OCSRC_PLL0_SYSCLK(7),
OCSEL_OCSRC_PLL1_OBSCLK,
};
static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = {
.name = "pll0_obsclk",
.parent_names = da850_pll0_obsclk_parent_names,
.num_parents = ARRAY_SIZE(da850_pll0_obsclk_parent_names),
.table = da850_pll0_obsclk_table,
.ocsrc_mask = GENMASK(4, 0),
};
int da850_pll0_init(struct device *dev, void __iomem *base)
{
struct clk *clk;
davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base);
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0");
clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1");
clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc");
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc");
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc0");
clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc1");
davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
clk_register_clkdev(clk, "pll0_sysclk6", "da850-psc0");
davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk",
CLK_IS_CRITICAL, 1, 1);
clk_register_clkdev(clk, NULL, "i2c_davinci.1");
clk_register_clkdev(clk, "timer0", NULL);
clk_register_clkdev(clk, NULL, "davinci-wdt");
davinci_pll_obsclk_register(dev, &da850_pll0_obsclk_info, base);
return 0;
}
static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = {
&pll0_sysclk1,
&pll0_sysclk2,
&pll0_sysclk3,
&pll0_sysclk4,
&pll0_sysclk5,
&pll0_sysclk6,
&pll0_sysclk7,
NULL
};
int of_da850_pll0_init(struct device *dev, void __iomem *base)
{
return of_davinci_pll_init(dev, &da850_pll0_info,
&da850_pll0_obsclk_info,
da850_pll0_sysclk_info, 7, base);
}
static const struct davinci_pll_clk_info da850_pll1_info = {
.name = "pll1",
.unlock_reg = CFGCHIP(3),
.unlock_mask = CFGCHIP3_PLL1_MASTER_LOCK,
.pllm_mask = GENMASK(4, 0),
.pllm_min = 4,
.pllm_max = 32,
.pllout_min_rate = 300000000,
.pllout_max_rate = 600000000,
.flags = PLL_HAS_POSTDIV,
};
SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0);
SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0);
static const char * const da850_pll1_obsclk_parent_names[] = {
"oscin",
"pll1_sysclk1",
"pll1_sysclk2",
"pll1_sysclk3",
};
static u32 da850_pll1_obsclk_table[] = {
OCSEL_OCSRC_OSCIN,
OCSEL_OCSRC_PLL1_SYSCLK(1),
OCSEL_OCSRC_PLL1_SYSCLK(2),
OCSEL_OCSRC_PLL1_SYSCLK(3),
};
static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = {
.name = "pll1_obsclk",
.parent_names = da850_pll1_obsclk_parent_names,
.num_parents = ARRAY_SIZE(da850_pll1_obsclk_parent_names),
.table = da850_pll1_obsclk_table,
.ocsrc_mask = GENMASK(4, 0),
};
int da850_pll1_init(struct device *dev, void __iomem *base)
{
struct clk *clk;
davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base);
davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc");
davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
davinci_pll_obsclk_register(dev, &da850_pll1_obsclk_info, base);
return 0;
}
static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = {
&pll1_sysclk1,
&pll1_sysclk2,
&pll1_sysclk3,
NULL
};
int of_da850_pll1_init(struct device *dev, void __iomem *base)
{
return of_davinci_pll_init(dev, &da850_pll1_info,
&da850_pll1_obsclk_info,
da850_pll1_sysclk_info, 3, base);
}
// SPDX-License-Identifier: GPL-2.0
/*
* PLL clock descriptions for TI DM355
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/bitops.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/types.h>
#include "pll.h"
static const struct davinci_pll_clk_info dm355_pll1_info = {
.name = "pll1",
.pllm_mask = GENMASK(7, 0),
.pllm_min = 92,
.pllm_max = 184,
.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED |
PLL_PREDIV_FIXED8 | PLL_HAS_POSTDIV |
PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
};
SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
int dm355_pll1_init(struct device *dev, void __iomem *base)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
clk_register_clkdev(clk, "pll1_sysclk2", "dm355-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
clk_register_clkdev(clk, "pll1_sysclk3", "dm355-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
clk_register_clkdev(clk, "pll1_sysclk4", "dm355-psc");
clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
return 0;
}
static const struct davinci_pll_clk_info dm355_pll2_info = {
.name = "pll2",
.pllm_mask = GENMASK(7, 0),
.pllm_min = 92,
.pllm_max = 184,
.flags = PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED | PLL_HAS_POSTDIV |
PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
};
SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
int dm355_pll2_init(struct device *dev, void __iomem *base)
{
davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base);
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
return 0;
}
// SPDX-License-Identifier: GPL-2.0
/*
* PLL clock descriptions for TI DM365
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/bitops.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "pll.h"
#define OCSEL_OCSRC_ENABLE 0
static const struct davinci_pll_clk_info dm365_pll1_info = {
.name = "pll1",
.pllm_mask = GENMASK(9, 0),
.pllm_min = 1,
.pllm_max = 1023,
.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
PLL_POSTDIV_ALWAYS_ENABLED | PLL_PLLM_2X,
};
SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(5, pll1_sysclk5, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(6, pll1_sysclk6, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(7, pll1_sysclk7, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(8, pll1_sysclk8, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(9, pll1_sysclk9, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
/*
* This is a bit of a hack to make OCSEL[OCSRC] on DM365 look like OCSEL[OCSRC]
* on DA850. On DM365, OCSEL[OCSRC] is just an enable/disable bit instead of a
* multiplexer. By modeling it as a single parent mux clock, the clock code will
* still do the right thing in this case.
*/
static const char * const dm365_pll_obsclk_parent_names[] = {
"oscin",
};
static u32 dm365_pll_obsclk_table[] = {
OCSEL_OCSRC_ENABLE,
};
static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
.name = "pll1_obsclk",
.parent_names = dm365_pll_obsclk_parent_names,
.num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
.table = dm365_pll_obsclk_table,
.ocsrc_mask = BIT(4),
};
int dm365_pll1_init(struct device *dev, void __iomem *base)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
clk_register_clkdev(clk, "pll1_sysclk3", "dm365-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
clk_register_clkdev(clk, "pll1_sysclk5", "dm365-psc");
davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
davinci_pll_sysclk_register(dev, &pll1_sysclk7, base);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
clk_register_clkdev(clk, "pll1_sysclk8", "dm365-psc");
davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
davinci_pll_obsclk_register(dev, &dm365_pll1_obsclk_info, base);
return 0;
}
static const struct davinci_pll_clk_info dm365_pll2_info = {
.name = "pll2",
.pllm_mask = GENMASK(9, 0),
.pllm_min = 1,
.pllm_max = 1023,
.flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV | PLL_POSTDIV_ALWAYS_ENABLED |
PLL_PLLM_2X,
};
SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(3, pll2_sysclk3, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(4, pll2_sysclk4, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(5, pll2_sysclk5, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
.name = "pll2_obsclk",
.parent_names = dm365_pll_obsclk_parent_names,
.num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
.table = dm365_pll_obsclk_table,
.ocsrc_mask = BIT(4),
};
int dm365_pll2_init(struct device *dev, void __iomem *base)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base);
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
clk = davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
davinci_pll_sysclk_register(dev, &pll2_sysclk3, base);
clk = davinci_pll_sysclk_register(dev, &pll2_sysclk4, base);
clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
davinci_pll_sysclk_register(dev, &pll2_sysclk5, base);
davinci_pll_auxclk_register(dev, "pll2_auxclk", base);
davinci_pll_obsclk_register(dev, &dm365_pll2_obsclk_info, base);
return 0;
}
// SPDX-License-Identifier: GPL-2.0
/*
* PLL clock descriptions for TI DM644X
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/bitops.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/types.h>
#include "pll.h"
static const struct davinci_pll_clk_info dm644x_pll1_info = {
.name = "pll1",
.pllm_mask = GENMASK(4, 0),
.pllm_min = 1,
.pllm_max = 32,
.pllout_min_rate = 400000000,
.pllout_max_rate = 600000000, /* 810MHz @ 1.3V, -810 only */
.flags = PLL_HAS_CLKMODE | PLL_HAS_POSTDIV,
};
SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
int dm644x_pll1_init(struct device *dev, void __iomem *base)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
clk_register_clkdev(clk, "pll1_sysclk2", "dm644x-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
clk_register_clkdev(clk, "pll1_sysclk3", "dm644x-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
clk_register_clkdev(clk, "pll1_sysclk5", "dm644x-psc");
clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
clk_register_clkdev(clk, "pll1_auxclk", "dm644x-psc");
davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
return 0;
}
static const struct davinci_pll_clk_info dm644x_pll2_info = {
.name = "pll2",
.pllm_mask = GENMASK(4, 0),
.pllm_min = 1,
.pllm_max = 32,
.pllout_min_rate = 400000000,
.pllout_max_rate = 900000000,
.flags = PLL_HAS_POSTDIV | PLL_POSTDIV_FIXED_DIV,
};
SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
int dm644x_pll2_init(struct device *dev, void __iomem *base)
{
davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base);
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
return 0;
}
// SPDX-License-Identifier: GPL-2.0
/*
* PLL clock descriptions for TI DM646X
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/types.h>
#include "pll.h"
static const struct davinci_pll_clk_info dm646x_pll1_info = {
.name = "pll1",
.pllm_mask = GENMASK(4, 0),
.pllm_min = 14,
.pllm_max = 32,
.flags = PLL_HAS_CLKMODE,
};
SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
SYSCLK(4, pll1_sysclk4, pll1_pllen, 4, 0);
SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, 0);
SYSCLK(6, pll1_sysclk6, pll1_pllen, 4, 0);
SYSCLK(8, pll1_sysclk8, pll1_pllen, 4, 0);
SYSCLK(9, pll1_sysclk9, pll1_pllen, 4, 0);
int dm646x_pll1_init(struct device *dev, void __iomem *base)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk_register_clkdev(clk, "pll1_sysclk1", "dm646x-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
clk_register_clkdev(clk, "pll1_sysclk2", "dm646x-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
clk_register_clkdev(clk, "pll1_sysclk3", "dm646x-psc");
clk_register_clkdev(clk, NULL, "davinci-wdt");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
clk_register_clkdev(clk, "pll1_sysclk4", "dm646x-psc");
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
clk_register_clkdev(clk, "pll1_sysclk5", "dm646x-psc");
davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
return 0;
}
static const struct davinci_pll_clk_info dm646x_pll2_info = {
.name = "pll2",
.pllm_mask = GENMASK(4, 0),
.pllm_min = 14,
.pllm_max = 32,
.flags = 0,
};
SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
int dm646x_pll2_init(struct device *dev, void __iomem *base)
{
davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base);
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
return 0;
}
This diff is collapsed.
// SPDX-License-Identifier: GPL-2.0
/*
* Clock driver for TI Davinci PSC controllers
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#ifndef __CLK_DAVINCI_PLL_H___
#define __CLK_DAVINCI_PLL_H___
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/types.h>
#define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */
#define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */
#define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */
#define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */
#define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */
#define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */
#define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */
#define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */
#define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */
#define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */
/** davinci_pll_clk_info - controller-specific PLL info
* @name: The name of the PLL
* @unlock_reg: Option CFGCHIP register for unlocking PLL
* @unlock_mask: Bitmask used with @unlock_reg
* @pllm_mask: Bitmask for PLLM[PLLM] value
* @pllm_min: Minimum allowable value for PLLM[PLLM]
* @pllm_max: Maximum allowable value for PLLM[PLLM]
* @pllout_min_rate: Minimum allowable rate for PLLOUT
* @pllout_max_rate: Maximum allowable rate for PLLOUT
* @flags: Bitmap of PLL_* flags.
*/
struct davinci_pll_clk_info {
const char *name;
u32 unlock_reg;
u32 unlock_mask;
u32 pllm_mask;
u32 pllm_min;
u32 pllm_max;
unsigned long pllout_min_rate;
unsigned long pllout_max_rate;
u32 flags;
};
#define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */
#define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */
#define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */
/** davinci_pll_sysclk_info - SYSCLKn-specific info
* @name: The name of the clock
* @parent_name: The name of the parent clock
* @id: "n" in "SYSCLKn"
* @ratio_width: Width (in bits) of RATIO in PLLDIVn register
* @flags: Bitmap of SYSCLK_* flags.
*/
struct davinci_pll_sysclk_info {
const char *name;
const char *parent_name;
u32 id;
u32 ratio_width;
u32 flags;
};
#define SYSCLK(i, n, p, w, f) \
static const struct davinci_pll_sysclk_info n = { \
.name = #n, \
.parent_name = #p, \
.id = (i), \
.ratio_width = (w), \
.flags = (f), \
}
/** davinci_pll_obsclk_info - OBSCLK-specific info
* @name: The name of the clock
* @parent_names: Array of names of the parent clocks
* @num_parents: Length of @parent_names
* @table: Array of values to write to OCSEL[OCSRC] cooresponding to
* @parent_names
* @ocsrc_mask: Bitmask for OCSEL[OCSRC]
*/
struct davinci_pll_obsclk_info {
const char *name;
const char * const *parent_names;
u8 num_parents;
u32 *table;
u32 ocsrc_mask;
};
struct clk *davinci_pll_clk_register(struct device *dev,
const struct davinci_pll_clk_info *info,
const char *parent_name,
void __iomem *base);
struct clk *davinci_pll_auxclk_register(struct device *dev,
const char *name,
void __iomem *base);
struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
const char *name,
void __iomem *base);
struct clk *
davinci_pll_obsclk_register(struct device *dev,
const struct davinci_pll_obsclk_info *info,
void __iomem *base);
struct clk *
davinci_pll_sysclk_register(struct device *dev,
const struct davinci_pll_sysclk_info *info,
void __iomem *base);
int of_davinci_pll_init(struct device *dev,
const struct davinci_pll_clk_info *info,
const struct davinci_pll_obsclk_info *obsclk_info,
const struct davinci_pll_sysclk_info **div_info,
u8 max_sysclk_id,
void __iomem *base);
/* Platform-specific callbacks */
int da830_pll_init(struct device *dev, void __iomem *base);
int da850_pll0_init(struct device *dev, void __iomem *base);
int da850_pll1_init(struct device *dev, void __iomem *base);
int of_da850_pll0_init(struct device *dev, void __iomem *base);
int of_da850_pll1_init(struct device *dev, void __iomem *base);
int dm355_pll1_init(struct device *dev, void __iomem *base);
int dm355_pll2_init(struct device *dev, void __iomem *base);
int dm365_pll1_init(struct device *dev, void __iomem *base);
int dm365_pll2_init(struct device *dev, void __iomem *base);
int dm644x_pll1_init(struct device *dev, void __iomem *base);
int dm644x_pll2_init(struct device *dev, void __iomem *base);
int dm646x_pll1_init(struct device *dev, void __iomem *base);
int dm646x_pll2_init(struct device *dev, void __iomem *base);
#endif /* __CLK_DAVINCI_PLL_H___ */
// SPDX-License-Identifier: GPL-2.0
/*
* PSC clock descriptions for TI DA830/OMAP-L137/AM17XX
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "psc.h"
LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
LPSC_CLKDEV1(mmcsd_clkdev, NULL, "da830-mmc.0");
LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
static const struct davinci_lpsc_clk_info da830_psc0_info[] = {
LPSC(0, 0, tpcc, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(3, 0, aemif, pll0_sysclk3, NULL, LPSC_ALWAYS_ENABLED),
LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0),
LPSC(5, 0, mmcsd, pll0_sysclk2, mmcsd_clkdev, 0),
LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(8, 0, secu_mgr, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0),
LPSC(10, 0, scr0_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(11, 0, scr1_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(12, 0, scr2_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(13, 0, pruss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(14, 0, arm, pll0_sysclk6, NULL, LPSC_ALWAYS_ENABLED),
{ }
};
static int da830_psc0_init(struct device *dev, void __iomem *base)
{
return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base);
}
static struct clk_bulk_data da830_psc0_parent_clks[] = {
{ .id = "pll0_sysclk2" },
{ .id = "pll0_sysclk3" },
{ .id = "pll0_sysclk4" },
{ .id = "pll0_sysclk6" },
};
const struct davinci_psc_init_data da830_psc0_init_data = {
.parent_clks = da830_psc0_parent_clks,
.num_parent_clks = ARRAY_SIZE(da830_psc0_parent_clks),
.psc_init = &da830_psc0_init,
};
LPSC_CLKDEV2(usb0_clkdev, NULL, "musb-da8xx",
NULL, "cppi41-dmaengine");
LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
/* REVISIT: gpio-davinci.c should be modified to drop con_id */
LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
"fck", "davinci_mdio.0");
LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1");
LPSC_CLKDEV1(mcasp2_clkdev, NULL, "davinci-mcasp.2");
LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2");
LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0");
LPSC_CLKDEV2(pwm_clkdev, "fck", "ehrpwm.0",
"fck", "ehrpwm.1");
LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0",
"fck", "ecap.1",
"fck", "ecap.2");
LPSC_CLKDEV2(eqep_clkdev, NULL, "eqep.0",
NULL, "eqep.1");
static const struct davinci_lpsc_clk_info da830_psc1_info[] = {
LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0),
LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0),
LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0),
LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0),
LPSC(6, 0, emif3, pll0_sysclk5, NULL, LPSC_ALWAYS_ENABLED),
LPSC(7, 0, mcasp0, pll0_sysclk2, mcasp0_clkdev, 0),
LPSC(8, 0, mcasp1, pll0_sysclk2, mcasp1_clkdev, 0),
LPSC(9, 0, mcasp2, pll0_sysclk2, mcasp2_clkdev, 0),
LPSC(10, 0, spi1, pll0_sysclk2, spi1_clkdev, 0),
LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0),
LPSC(12, 0, uart1, pll0_sysclk2, uart1_clkdev, 0),
LPSC(13, 0, uart2, pll0_sysclk2, uart2_clkdev, 0),
LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0),
LPSC(17, 0, pwm, pll0_sysclk2, pwm_clkdev, 0),
LPSC(20, 0, ecap, pll0_sysclk2, ecap_clkdev, 0),
LPSC(21, 0, eqep, pll0_sysclk2, eqep_clkdev, 0),
{ }
};
static int da830_psc1_init(struct device *dev, void __iomem *base)
{
return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base);
}
static struct clk_bulk_data da830_psc1_parent_clks[] = {
{ .id = "pll0_sysclk2" },
{ .id = "pll0_sysclk4" },
{ .id = "pll0_sysclk5" },
};
const struct davinci_psc_init_data da830_psc1_init_data = {
.parent_clks = da830_psc1_parent_clks,
.num_parent_clks = ARRAY_SIZE(da830_psc1_parent_clks),
.psc_init = &da830_psc1_init,
};
// SPDX-License-Identifier: GPL-2.0
/*
* PSC clock descriptions for TI DA850/OMAP-L138/AM18XX
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/types.h>
#include "psc.h"
LPSC_CLKDEV2(emifa_clkdev, NULL, "ti-aemif",
"aemif", "davinci_nand.0");
LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0");
LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
/* REVISIT: used dev_id instead of con_id */
LPSC_CLKDEV1(arm_clkdev, "arm", NULL);
LPSC_CLKDEV1(dsp_clkdev, NULL, "davinci-rproc.0");
static const struct davinci_lpsc_clk_info da850_psc0_info[] = {
LPSC(0, 0, tpcc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(3, 0, emifa, async1, emifa_clkdev, 0),
LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0),
LPSC(5, 0, mmcsd0, pll0_sysclk2, mmcsd0_clkdev, 0),
LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0),
LPSC(13, 0, pruss, pll0_sysclk2, NULL, 0),
LPSC(14, 0, arm, pll0_sysclk6, arm_clkdev, LPSC_ALWAYS_ENABLED | LPSC_SET_RATE_PARENT),
LPSC(15, 1, dsp, pll0_sysclk1, dsp_clkdev, LPSC_FORCE | LPSC_LOCAL_RESET),
{ }
};
LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
NULL, "musb-da8xx",
NULL, "cppi41-dmaengine");
LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
/* REVISIT: gpio-davinci.c should be modified to drop con_id */
LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
"fck", "davinci_mdio.0");
LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
LPSC_CLKDEV1(sata_clkdev, "fck", "ahci_da850");
LPSC_CLKDEV1(vpif_clkdev, NULL, "vpif");
LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2");
LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0");
LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1");
LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0");
LPSC_CLKDEV3(ehrpwm_clkdev, "fck", "ehrpwm.0",
"fck", "ehrpwm.1",
NULL, "da830-tbclksync");
LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1");
LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0",
"fck", "ecap.1",
"fck", "ecap.2");
static int da850_psc0_init(struct device *dev, void __iomem *base)
{
return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base);
}
static int of_da850_psc0_init(struct device *dev, void __iomem *base)
{
return of_davinci_psc_clk_init(dev, da850_psc0_info, 16, base);
}
static struct clk_bulk_data da850_psc0_parent_clks[] = {
{ .id = "pll0_sysclk1" },
{ .id = "pll0_sysclk2" },
{ .id = "pll0_sysclk4" },
{ .id = "pll0_sysclk6" },
{ .id = "async1" },
};
const struct davinci_psc_init_data da850_psc0_init_data = {
.parent_clks = da850_psc0_parent_clks,
.num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks),
.psc_init = &da850_psc0_init,
};
const struct davinci_psc_init_data of_da850_psc0_init_data = {
.parent_clks = da850_psc0_parent_clks,
.num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks),
.psc_init = &of_da850_psc0_init,
};
static const struct davinci_lpsc_clk_info da850_psc1_info[] = {
LPSC(0, 0, tpcc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0),
LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0),
LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0),
LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0),
LPSC(6, 0, ddr, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(7, 0, mcasp0, async3, mcasp0_clkdev, 0),
LPSC(8, 0, sata, pll0_sysclk2, sata_clkdev, LPSC_FORCE),
LPSC(9, 0, vpif, pll0_sysclk2, vpif_clkdev, 0),
LPSC(10, 0, spi1, async3, spi1_clkdev, 0),
LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0),
LPSC(12, 0, uart1, async3, uart1_clkdev, 0),
LPSC(13, 0, uart2, async3, uart2_clkdev, 0),
LPSC(14, 0, mcbsp0, async3, mcbsp0_clkdev, 0),
LPSC(15, 0, mcbsp1, async3, mcbsp1_clkdev, 0),
LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0),
LPSC(17, 0, ehrpwm, async3, ehrpwm_clkdev, 0),
LPSC(18, 0, mmcsd1, pll0_sysclk2, mmcsd1_clkdev, 0),
LPSC(20, 0, ecap, async3, ecap_clkdev, 0),
LPSC(21, 0, tptc2, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
{ }
};
static int da850_psc1_init(struct device *dev, void __iomem *base)
{
return davinci_psc_register_clocks(dev, da850_psc1_info, 32, base);
}
static int of_da850_psc1_init(struct device *dev, void __iomem *base)
{
return of_davinci_psc_clk_init(dev, da850_psc1_info, 32, base);
}
static struct clk_bulk_data da850_psc1_parent_clks[] = {
{ .id = "pll0_sysclk2" },
{ .id = "pll0_sysclk4" },
{ .id = "async3" },
};
const struct davinci_psc_init_data da850_psc1_init_data = {
.parent_clks = da850_psc1_parent_clks,
.num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks),
.psc_init = &da850_psc1_init,
};
const struct davinci_psc_init_data of_da850_psc1_init_data = {
.parent_clks = da850_psc1_parent_clks,
.num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks),
.psc_init = &of_da850_psc1_init,
};
// SPDX-License-Identifier: GPL-2.0
/*
* PSC clock descriptions for TI DaVinci DM355
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "psc.h"
LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "dm6441-mmc.1");
LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1");
LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2");
LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL);
LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "dm6441-mmc.0");
LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0");
LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
/* REVISIT: gpio-davinci.c should be modified to drop con_id */
LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL);
static const struct davinci_lpsc_clk_info dm355_psc_info[] = {
LPSC(0, 0, vpss_master, pll1_sysclk4, vpss_master_clkdev, 0),
LPSC(1, 0, vpss_slave, pll1_sysclk4, vpss_slave_clkdev, 0),
LPSC(5, 0, timer3, pll1_auxclk, NULL, 0),
LPSC(6, 0, spi1, pll1_sysclk2, spi1_clkdev, 0),
LPSC(7, 0, mmcsd1, pll1_sysclk2, mmcsd1_clkdev, 0),
LPSC(8, 0, asp1, pll1_sysclk2, NULL, 0),
LPSC(9, 0, usb, pll1_sysclk2, usb_clkdev, 0),
LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0),
LPSC(11, 0, spi2, pll1_sysclk2, spi2_clkdev, 0),
LPSC(12, 0, rto, pll1_auxclk, NULL, 0),
LPSC(14, 0, aemif, pll1_sysclk2, aemif_clkdev, 0),
LPSC(15, 0, mmcsd0, pll1_sysclk2, mmcsd0_clkdev, 0),
LPSC(17, 0, asp0, pll1_sysclk2, NULL, 0),
LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
LPSC(20, 0, uart1, pll1_auxclk, uart1_clkdev, 0),
LPSC(21, 0, uart2, pll1_sysclk2, uart2_clkdev, 0),
LPSC(22, 0, spi0, pll1_sysclk2, spi0_clkdev, 0),
LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
LPSC(26, 0, gpio, pll1_sysclk2, gpio_clkdev, 0),
LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
/* REVISIT: why can't this be disabled? */
LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
LPSC(31, 0, arm, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED),
LPSC(40, 0, mjcp, pll1_sysclk1, NULL, 0),
LPSC(41, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
{ }
};
static int dm355_psc_init(struct device *dev, void __iomem *base)
{
return davinci_psc_register_clocks(dev, dm355_psc_info, 42, base);
}
static struct clk_bulk_data dm355_psc_parent_clks[] = {
{ .id = "pll1_sysclk1" },
{ .id = "pll1_sysclk2" },
{ .id = "pll1_sysclk3" },
{ .id = "pll1_sysclk4" },
{ .id = "pll1_auxclk" },
};
const struct davinci_psc_init_data dm355_psc_init_data = {
.parent_clks = dm355_psc_parent_clks,
.num_parent_clks = ARRAY_SIZE(dm355_psc_parent_clks),
.psc_init = &dm355_psc_init,
};
// SPDX-License-Identifier: GPL-2.0
/*
* PSC clock descriptions for TI DaVinci DM365
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "psc.h"
LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1");
LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp");
LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2");
LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL);
LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0");
LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
/* REVISIT: gpio-davinci.c should be modified to drop con_id */
LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
LPSC_CLKDEV1(spi3_clkdev, NULL, "spi_davinci.3");
LPSC_CLKDEV1(spi4_clkdev, NULL, "spi_davinci.4");
LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
"fck", "davinci_mdio.0");
LPSC_CLKDEV1(voice_codec_clkdev, NULL, "davinci_voicecodec");
LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL);
LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
LPSC(1, 0, vpss_slave, pll1_sysclk5, vpss_slave_clkdev, 0),
LPSC(5, 0, timer3, pll1_auxclk, NULL, 0),
LPSC(6, 0, spi1, pll1_sysclk4, spi1_clkdev, 0),
LPSC(7, 0, mmcsd1, pll1_sysclk4, mmcsd1_clkdev, 0),
LPSC(8, 0, asp0, pll1_sysclk4, asp0_clkdev, 0),
LPSC(9, 0, usb, pll1_auxclk, usb_clkdev, 0),
LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0),
LPSC(11, 0, spi2, pll1_sysclk4, spi2_clkdev, 0),
LPSC(12, 0, rto, pll1_sysclk4, NULL, 0),
LPSC(14, 0, aemif, pll1_sysclk4, aemif_clkdev, 0),
LPSC(15, 0, mmcsd0, pll1_sysclk8, mmcsd0_clkdev, 0),
LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
LPSC(20, 0, uart1, pll1_sysclk4, uart1_clkdev, 0),
LPSC(22, 0, spi0, pll1_sysclk4, spi0_clkdev, 0),
LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
LPSC(26, 0, gpio, pll1_sysclk4, gpio_clkdev, 0),
LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
/* REVISIT: why can't this be disabled? */
LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
LPSC(31, 0, arm, pll2_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(38, 0, spi3, pll1_sysclk4, spi3_clkdev, 0),
LPSC(39, 0, spi4, pll1_auxclk, spi4_clkdev, 0),
LPSC(40, 0, emac, pll2_sysclk4, emac_clkdev, 0),
LPSC(44, 1, voice_codec, pll1_sysclk3, voice_codec_clkdev, 0),
LPSC(46, 1, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
LPSC(50, 0, mjcp, pll1_sysclk3, NULL, 0),
{ }
};
static int dm365_psc_init(struct device *dev, void __iomem *base)
{
return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base);
}
static struct clk_bulk_data dm365_psc_parent_clks[] = {
{ .id = "pll1_sysclk1" },
{ .id = "pll1_sysclk3" },
{ .id = "pll1_sysclk4" },
{ .id = "pll1_sysclk5" },
{ .id = "pll1_sysclk8" },
{ .id = "pll2_sysclk2" },
{ .id = "pll2_sysclk4" },
{ .id = "pll1_auxclk" },
};
const struct davinci_psc_init_data dm365_psc_init_data = {
.parent_clks = dm365_psc_parent_clks,
.num_parent_clks = ARRAY_SIZE(dm365_psc_parent_clks),
.psc_init = &dm365_psc_init,
};
// SPDX-License-Identifier: GPL-2.0
/*
* PSC clock descriptions for TI DaVinci DM644x
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "psc.h"
LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
"fck", "davinci_mdio.0");
LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
LPSC_CLKDEV1(ide_clkdev, NULL, "palm_bk3710");
LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL);
LPSC_CLKDEV1(mmcsd_clkdev, NULL, "dm6441-mmc.0");
LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp");
LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
/* REVISIT: gpio-davinci.c should be modified to drop con_id */
LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
static const struct davinci_lpsc_clk_info dm644x_psc_info[] = {
LPSC(0, 0, vpss_master, pll1_sysclk3, vpss_master_clkdev, 0),
LPSC(1, 0, vpss_slave, pll1_sysclk3, vpss_slave_clkdev, 0),
LPSC(6, 0, emac, pll1_sysclk5, emac_clkdev, 0),
LPSC(9, 0, usb, pll1_sysclk5, usb_clkdev, 0),
LPSC(10, 0, ide, pll1_sysclk5, ide_clkdev, 0),
LPSC(11, 0, vlynq, pll1_sysclk5, NULL, 0),
LPSC(14, 0, aemif, pll1_sysclk5, aemif_clkdev, 0),
LPSC(15, 0, mmcsd, pll1_sysclk5, mmcsd_clkdev, 0),
LPSC(17, 0, asp0, pll1_sysclk5, asp0_clkdev, 0),
LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
LPSC(20, 0, uart1, pll1_auxclk, uart1_clkdev, 0),
LPSC(21, 0, uart2, pll1_auxclk, uart2_clkdev, 0),
LPSC(22, 0, spi, pll1_sysclk5, NULL, 0),
LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
LPSC(26, 0, gpio, pll1_sysclk5, gpio_clkdev, 0),
LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
/* REVISIT: why can't this be disabled? */
LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
LPSC(31, 0, arm, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
/* REVISIT how to disable? */
LPSC(39, 1, dsp, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED),
/* REVISIT how to disable? */
LPSC(40, 1, vicp, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
{ }
};
static int dm644x_psc_init(struct device *dev, void __iomem *base)
{
return davinci_psc_register_clocks(dev, dm644x_psc_info, 41, base);
}
static struct clk_bulk_data dm644x_psc_parent_clks[] = {
{ .id = "pll1_sysclk1" },
{ .id = "pll1_sysclk2" },
{ .id = "pll1_sysclk3" },
{ .id = "pll1_sysclk5" },
{ .id = "pll1_auxclk" },
};
const struct davinci_psc_init_data dm644x_psc_init_data = {
.parent_clks = dm644x_psc_parent_clks,
.num_parent_clks = ARRAY_SIZE(dm644x_psc_parent_clks),
.psc_init = &dm644x_psc_init,
};
// SPDX-License-Identifier: GPL-2.0
/*
* PSC clock descriptions for TI DaVinci DM646x
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "psc.h"
LPSC_CLKDEV1(ide_clkdev, NULL, "palm_bk3710");
LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
"fck", "davinci_mdio.0");
LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL);
LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1");
LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
/* REVISIT: gpio-davinci.c should be modified to drop con_id */
LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
static const struct davinci_lpsc_clk_info dm646x_psc_info[] = {
LPSC(0, 0, arm, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
/* REVISIT how to disable? */
LPSC(1, 0, dsp, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED),
LPSC(4, 0, edma_cc, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(5, 0, edma_tc0, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(6, 0, edma_tc1, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(7, 0, edma_tc2, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(8, 0, edma_tc3, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(10, 0, ide, pll1_sysclk4, ide_clkdev, 0),
LPSC(14, 0, emac, pll1_sysclk3, emac_clkdev, 0),
LPSC(16, 0, vpif0, ref_clk, NULL, LPSC_ALWAYS_ENABLED),
LPSC(17, 0, vpif1, ref_clk, NULL, LPSC_ALWAYS_ENABLED),
LPSC(21, 0, aemif, pll1_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED),
LPSC(22, 0, mcasp0, pll1_sysclk3, mcasp0_clkdev, 0),
LPSC(23, 0, mcasp1, pll1_sysclk3, mcasp1_clkdev, 0),
LPSC(26, 0, uart0, aux_clkin, uart0_clkdev, 0),
LPSC(27, 0, uart1, aux_clkin, uart1_clkdev, 0),
LPSC(28, 0, uart2, aux_clkin, uart2_clkdev, 0),
/* REVIST: disabling hangs system */
LPSC(29, 0, pwm0, pll1_sysclk3, NULL, LPSC_ALWAYS_ENABLED),
/* REVIST: disabling hangs system */
LPSC(30, 0, pwm1, pll1_sysclk3, NULL, LPSC_ALWAYS_ENABLED),
LPSC(31, 0, i2c, pll1_sysclk3, i2c_clkdev, 0),
LPSC(33, 0, gpio, pll1_sysclk3, gpio_clkdev, 0),
LPSC(34, 0, timer0, pll1_sysclk3, timer0_clkdev, LPSC_ALWAYS_ENABLED),
LPSC(35, 0, timer1, pll1_sysclk3, NULL, 0),
{ }
};
static int dm646x_psc_init(struct device *dev, void __iomem *base)
{
return davinci_psc_register_clocks(dev, dm646x_psc_info, 46, base);
}
static struct clk_bulk_data dm646x_psc_parent_clks[] = {
{ .id = "ref_clk" },
{ .id = "aux_clkin" },
{ .id = "pll1_sysclk1" },
{ .id = "pll1_sysclk2" },
{ .id = "pll1_sysclk3" },
{ .id = "pll1_sysclk4" },
{ .id = "pll1_sysclk5" },
};
const struct davinci_psc_init_data dm646x_psc_init_data = {
.parent_clks = dm646x_psc_parent_clks,
.num_parent_clks = ARRAY_SIZE(dm646x_psc_parent_clks),
.psc_init = &dm646x_psc_init,
};
This diff is collapsed.
// SPDX-License-Identifier: GPL-2.0
/*
* Clock driver for TI Davinci PSC controllers
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#ifndef __CLK_DAVINCI_PSC_H__
#define __CLK_DAVINCI_PSC_H__
#include <linux/clk-provider.h>
#include <linux/types.h>
/* PSC quirk flags */
#define LPSC_ALWAYS_ENABLED BIT(0) /* never disable this clock */
#define LPSC_SET_RATE_PARENT BIT(1) /* propagate set_rate to parent clock */
#define LPSC_FORCE BIT(2) /* requires MDCTL FORCE bit */
#define LPSC_LOCAL_RESET BIT(3) /* acts as reset provider */
struct davinci_lpsc_clkdev_info {
const char *con_id;
const char *dev_id;
};
#define LPSC_CLKDEV(c, d) { \
.con_id = (c), \
.dev_id = (d) \
}
#define LPSC_CLKDEV1(n, c, d) \
static const struct davinci_lpsc_clkdev_info n[] __initconst = { \
LPSC_CLKDEV((c), (d)), \
{ } \
}
#define LPSC_CLKDEV2(n, c1, d1, c2, d2) \
static const struct davinci_lpsc_clkdev_info n[] __initconst = { \
LPSC_CLKDEV((c1), (d1)), \
LPSC_CLKDEV((c2), (d2)), \
{ } \
}
#define LPSC_CLKDEV3(n, c1, d1, c2, d2, c3, d3) \
static const struct davinci_lpsc_clkdev_info n[] __initconst = { \
LPSC_CLKDEV((c1), (d1)), \
LPSC_CLKDEV((c2), (d2)), \
LPSC_CLKDEV((c3), (d3)), \
{ } \
}
/**
* davinci_lpsc_clk_info - LPSC module-specific clock information
* @name: the clock name
* @parent: the parent clock name
* @cdevs: optional array of clkdev lookup table info
* @md: the local module domain (LPSC id)
* @pd: the power domain id
* @flags: bitmask of LPSC_* flags
*/
struct davinci_lpsc_clk_info {
const char *name;
const char *parent;
const struct davinci_lpsc_clkdev_info *cdevs;
u32 md;
u32 pd;
unsigned long flags;
};
#define LPSC(m, d, n, p, c, f) \
{ \
.name = #n, \
.parent = #p, \
.cdevs = (c), \
.md = (m), \
.pd = (d), \
.flags = (f), \
}
int davinci_psc_register_clocks(struct device *dev,
const struct davinci_lpsc_clk_info *info,
u8 num_clks,
void __iomem *base);
int of_davinci_psc_clk_init(struct device *dev,
const struct davinci_lpsc_clk_info *info,
u8 num_clks,
void __iomem *base);
/* Device-specific data */
struct davinci_psc_init_data {
struct clk_bulk_data *parent_clks;
int num_parent_clks;
int (*psc_init)(struct device *dev, void __iomem *base);
};
extern const struct davinci_psc_init_data da830_psc0_init_data;
extern const struct davinci_psc_init_data da830_psc1_init_data;
extern const struct davinci_psc_init_data da850_psc0_init_data;
extern const struct davinci_psc_init_data da850_psc1_init_data;
extern const struct davinci_psc_init_data of_da850_psc0_init_data;
extern const struct davinci_psc_init_data of_da850_psc1_init_data;
extern const struct davinci_psc_init_data dm355_psc_init_data;
extern const struct davinci_psc_init_data dm365_psc_init_data;
extern const struct davinci_psc_init_data dm644x_psc_init_data;
extern const struct davinci_psc_init_data dm646x_psc_init_data;
#endif /* __CLK_DAVINCI_PSC_H__ */
......@@ -25,6 +25,8 @@ struct rockchip_mmc_clock {
void __iomem *reg;
int id;
int shift;
int cached_phase;
struct notifier_block clk_rate_change_nb;
};
#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
......@@ -58,6 +60,12 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
u16 degrees;
u32 delay_num = 0;
/* See the comment for rockchip_mmc_set_phase below */
if (!rate) {
pr_err("%s: invalid clk rate\n", __func__);
return -EINVAL;
}
raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
......@@ -84,6 +92,23 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
u32 raw_value;
u32 delay;
/*
* The below calculation is based on the output clock from
* MMC host to the card, which expects the phase clock inherits
* the clock rate from its parent, namely the output clock
* provider of MMC host. However, things may go wrong if
* (1) It is orphan.
* (2) It is assigned to the wrong parent.
*
* This check help debug the case (1), which seems to be the
* most likely problem we often face and which makes it difficult
* for people to debug unstable mmc tuning results.
*/
if (!rate) {
pr_err("%s: invalid clk rate\n", __func__);
return -EINVAL;
}
nineties = degrees / 90;
remainder = (degrees % 90);
......@@ -139,6 +164,41 @@ static const struct clk_ops rockchip_mmc_clk_ops = {
.set_phase = rockchip_mmc_set_phase,
};
#define to_rockchip_mmc_clock(x) \
container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb)
static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb,
unsigned long event, void *data)
{
struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb);
struct clk_notifier_data *ndata = data;
/*
* rockchip_mmc_clk is mostly used by mmc controllers to sample
* the intput data, which expects the fixed phase after the tuning
* process. However if the clock rate is changed, the phase is stale
* and may break the data sampling. So here we try to restore the phase
* for that case, except that
* (1) cached_phase is invaild since we inevitably cached it when the
* clock provider be reparented from orphan to its real parent in the
* first place. Otherwise we may mess up the initialization of MMC cards
* since we only set the default sample phase and drive phase later on.
* (2) the new coming rate is higher than the older one since mmc driver
* set the max-frequency to match the boards' ability but we can't go
* over the heads of that, otherwise the tests smoke out the issue.
*/
if (ndata->old_rate <= ndata->new_rate)
return NOTIFY_DONE;
if (event == PRE_RATE_CHANGE)
mmc_clock->cached_phase =
rockchip_mmc_get_phase(&mmc_clock->hw);
else if (mmc_clock->cached_phase != -EINVAL &&
event == POST_RATE_CHANGE)
rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);
return NOTIFY_DONE;
}
struct clk *rockchip_clk_register_mmc(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *reg, int shift)
......@@ -146,6 +206,7 @@ struct clk *rockchip_clk_register_mmc(const char *name,
struct clk_init_data init;
struct rockchip_mmc_clock *mmc_clock;
struct clk *clk;
int ret;
mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
if (!mmc_clock)
......@@ -162,8 +223,21 @@ struct clk *rockchip_clk_register_mmc(const char *name,
mmc_clock->shift = shift;
clk = clk_register(NULL, &mmc_clock->hw);
if (IS_ERR(clk))
kfree(mmc_clock);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto err_register;
}
mmc_clock->clk_rate_change_nb.notifier_call =
&rockchip_mmc_clk_rate_notify;
ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);
if (ret)
goto err_notifier;
return clk;
err_notifier:
clk_unregister(clk);
err_register:
kfree(mmc_clock);
return ERR_PTR(ret);
}
......@@ -387,7 +387,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 11, GFLAGS),
......
This diff is collapsed.
......@@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
......@@ -670,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(9), 7, GFLAGS,
&rk3399_uart3_fracmux),
COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(3), 4, GFLAGS),
......@@ -886,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(31), 8, GFLAGS),
/* sdio & sdmmc */
COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 13, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
......
......@@ -57,6 +57,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
struct clk_divider *div = NULL;
const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
*gate_ops = NULL;
int ret;
if (num_parents > 1) {
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
......@@ -74,8 +75,10 @@ static struct clk *rockchip_clk_register_branch(const char *name,
if (gate_offset >= 0) {
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
if (!gate) {
ret = -ENOMEM;
goto err_gate;
}
gate->flags = gate_flags;
gate->reg = base + gate_offset;
......@@ -86,8 +89,10 @@ static struct clk *rockchip_clk_register_branch(const char *name,
if (div_width > 0) {
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
if (!div) {
ret = -ENOMEM;
goto err_div;
}
div->flags = div_flags;
div->reg = base + muxdiv_offset;
......@@ -106,12 +111,19 @@ static struct clk *rockchip_clk_register_branch(const char *name,
gate ? &gate->hw : NULL, gate_ops,
flags);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto err_composite;
}
return clk;
err_composite:
kfree(div);
err_div:
kfree(gate);
err_gate:
kfree(mux);
return ERR_PTR(-ENOMEM);
return ERR_PTR(ret);
}
struct rockchip_clk_frac {
......@@ -291,8 +303,10 @@ static struct clk *rockchip_clk_register_frac_branch(
init.num_parents = child->num_parents;
mux_clk = clk_register(NULL, &frac_mux->hw);
if (IS_ERR(mux_clk))
if (IS_ERR(mux_clk)) {
kfree(frac);
return clk;
}
rockchip_clk_add_lookup(ctx, mux_clk, child->id);
......
......@@ -537,6 +537,8 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
init.parent_names = &reg_data->parent;
init.num_parents = 1;
init.flags = 0;
if (reg_data->flags & CLKF_SET_RATE_PARENT)
init.flags |= CLK_SET_RATE_PARENT;
init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
node->parent->name, node->name,
reg_data->offset, 0);
......
......@@ -76,6 +76,11 @@ enum {
#define CLKF_CORE (1 << 9)
#define CLKF_J_TYPE (1 << 10)
/* CLKCTRL flags */
#define CLKF_SW_SUP BIT(5)
#define CLKF_HW_SUP BIT(6)
#define CLKF_NO_IDLEST BIT(7)
#define CLK(dev, con, ck) \
{ \
.lk = { \
......@@ -185,10 +190,6 @@ extern const struct omap_clkctrl_data am438x_clkctrl_data[];
extern const struct omap_clkctrl_data dm814_clkctrl_data[];
extern const struct omap_clkctrl_data dm816_clkctrl_data[];
#define CLKF_SW_SUP BIT(0)
#define CLKF_HW_SUP BIT(1)
#define CLKF_NO_IDLEST BIT(2)
typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
......
This diff is collapsed.
......@@ -193,7 +193,6 @@
#define HCLK_VPU_PRE 324
#define HCLK_VIO_PRE 325
#define HCLK_VPU 326
#define HCLK_VIO 327
#define HCLK_BUS_PRE 328
#define HCLK_PERI_PRE 329
#define HCLK_H264 330
......
// SPDX-License-Identifier: GPL-2.0
/*
* clk-da8xx-cfgchip - TI DaVinci DA8xx CFGCHIP clock driver
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#ifndef __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__
#define __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__
#include <linux/regmap.h>
/**
* da8xx_cfgchip_clk_platform_data
* @cfgchip: CFGCHIP syscon regmap
*/
struct da8xx_cfgchip_clk_platform_data {
struct regmap *cfgchip;
};
#endif /* __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ */
This diff is collapsed.
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